PCB Layout

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Editor Overview

The PCB editor includes:

• Layer stack — Manage copper, silkscreen, mask, and mechanical layers
• Ratsnest — Visual guides showing unrouted connections
• 3D Viewer — Preview your board in 3D (Alt+3)
• Design rules — Configurable constraints for trace width, clearance, etc.
• DRC Rule Editor — Visual rule builder for creating and managing design rules with autocomplete and constraint panels

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AI Layer Control

Ask the AI to switch between PCB layers, apply layer presets, or toggle layer visibility directly from the chat. For example, “switch to the back copper layer” or “hide all silkscreen layers.” The AI uses dedicated tools (switch_layer, get_layers, apply_layer_preset, set_layer_visibility) to control the layer stack.

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Component Placement

After importing from the schematic (F8), arrange components on the board:

• Move components with M
• Rotate with R
• Flip to the back side with F
• Group related components together
• Keep high-frequency components close to their connections
• Align connectors with board edges

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AI Auto-Placement

Trace includes an AI-powered auto-placer that uses a graph neural network (GNN) combined with simulated annealing for placement optimization. The AI analyzes your schematic to understand component connectivity, signal flow, and relationships, then optimizes component positions.

• Import optimization — Import existing KiCad boards and let the AI optimize component placement, especially effective for boards where placement was done manually and could benefit from optimization
• Signal flow analysis — The GNN learns component connectivity patterns to place related components close together
• Constraint-aware — Respects board outline, keep-out zones, and mechanical constraints during optimization
• EMI-aware placement — The placer considers electromagnetic interference when positioning sensitive analog and high-speed digital components, keeping noisy components away from sensitive inputs (expanding)

You can ask the AI to place all components or just a specific group.

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How It Works

The placement engine uses a three-stage approach:

1. Graph encoding — Your schematic’s netlist is represented as a bipartite component-net graph. A Graph Attention Network (GAT) processes this graph to produce embeddings that capture each component’s connectivity context — which components it connects to, through how many nets, and what the topology looks like.
2. Guided simulated annealing — The GNN’s predictions bias the SA search: component selection probability is weighted by the GNN’s quality estimates, and move directions are informed by learned placement heuristics. The SA optimizer then iterates through move, swap, and rotate operations with Boltzmann acceptance.
3. Cost evaluation — Each placement candidate is scored on half-perimeter wire length (HPWL), component overlap, and boundary violations. The optimizer minimizes this composite cost over thousands of iterations.

This approach has been validated on 15 real-world KiCad PCBs ranging from 5 to 681 components, achieving measurable wire length improvements over unguided simulated annealing.

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Design Variants

Manage alternate board configurations without duplicating your project. Define variants to control which components are populated, swap values, or change footprints for different product SKUs, regions, or development stages. See the Design Variants page for details on creating variants, exporting with --variant, and importing Altium variants.

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Routing

Route traces manually or use the autorouter:

• Press X to start routing a trace
• Press V to place a via and switch layers
• The autorouter handles all connections automatically
• Manual routing gives you full control over trace paths

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Layer Stackup & Impedance Control

For controlled-impedance designs, Trace follows a stackup-first workflow:

1. Define the stackup — Set layer count, copper weight, and dielectric thickness for your board
2. Derive trace widths — Trace calculates trace widths for controlled impedance based on your stackup parameters
3. Lock before routing — Impedance-controlled widths are locked into net classes before routing begins, so traces maintain correct geometry throughout the layout

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Differential Pairs

Differential pairs (USB, LVDS, DDR, PCIe) are handled with dedicated constraints:

• Coupled routing — Diff pairs are routed together with controlled spacing enforced during routing
• Length matching — Intra-pair and inter-pair length matching to maintain signal timing
• Reference plane tracking — Return paths are tracked to keep them continuous across the reference plane, avoiding splits that degrade signal integrity

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Signal Integrity Considerations

• High-speed nets are identified from the schematic and flagged for priority routing
• Via stitching near signal transitions between layers
• Copper pour optimization for thermal and EMI performance

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Design Rule Check

Run DRC to verify your layout meets manufacturing constraints:

• Minimum trace width and spacing
• Via drill sizes and annular rings
• Courtyard clearances between components
• Board edge clearances
• Impedance rule violations
• Unrouted nets
• Track endpoints not centered on via — Detects misaligned track-to-via connections from the interactive router (new in Trace 1.3)

Access via Inspect → Design Rules Checker or Ctrl+Shift+D. For creating and managing design rules visually, see the DRC Rule Editor.

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Copper Pours

Add copper fill zones for ground planes and power distribution:

1. Press Ctrl+Shift+Z to add a filled zone
2. Select the net (usually GND)
3. Draw the zone boundary
4. Press B to fill all zones

Zones with different priorities can now be merged, allowing overlapping copper pours to combine when they share the same net. Negative outset values are supported for insetting zone boundaries, and negative silkscreen clearance values are allowed for designs that intentionally overlap silkscreen and copper.

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Track & Via Properties

The Track & Via Properties dialog includes backdrill sizes for controlled-depth drilling. Backdrill removes unused via stubs that can cause signal reflections on high-speed designs.

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Manufacturing Export

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IPC-2581

IPC-2581 export includes several enhancements:

• BomRef and AvlRef elements — Approved vendor list references in the output
• Board profile cutouts — Internal cutouts included in the board profile
• Multi-outline geometry merging — Complex component outlines merged correctly
• Pin 1 orientation inference — pinOneOrientation automatically inferred from pin 1 position
• Stable reference designators — Synthesized stable refdes for components with empty references
• Schematic revision for BOM — Uses schematic revision metadata in BOM output

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Standard Exports

Generate Gerbers, drill files, pick-and-place files, and BOMs. Package into fab-ready ZIP archives. Export STEP files for mechanical CAD integration. All exports support the --variant flag for design variant filtering.

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Case Design Import

Import your enclosure design to use as a reference layer while designing your PCB. This lets you align mounting holes, connectors, and components with your physical case before manufacturing.

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Supported Formats

• DXF — 2D outline from CAD software (Fusion 360, SolidWorks, FreeCAD)
• STEP/STP — 3D models for full enclosure visualization

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Use Cases

• Align USB ports, buttons, and LEDs with case cutouts
• Position mounting holes to match enclosure standoffs
• Verify antenna keep-out zones for Bluetooth/WiFi
• Check battery compartment clearances
• Ensure component height fits within enclosure

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Importing from Other EDA Tools

Trace can import PCB layouts from Cadence Allegro (including v18+ binary format), Mentor PADS (ASCII format), and Altium Designer. See the Importing from Other EDA Tools guide for details.