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Documentation Index

Fetch the complete documentation index at: https://docs.buildwithtrace.com/llms.txt

Use this file to discover all available pages before exploring further.

This is a living document. Features are prioritized by community demand, beta tester feedback, and strategic alignment.

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Submit a Request

Discord

Post in #feature-requests and upvote others’ ideas

Email

hello@buildwithtrace.com

Beta Feedback

Submit from the dashboard (earns points)
Want your request prioritized? Join the beta program — beta members get free Trace access in exchange for active feedback. Engineers who test features and report issues get their requests fast-tracked.
Legend: Shipped · In Progress · Planned · Requested

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Coming Soon

Features currently in active development with target release windows:
FeatureTargetDescription
PCB MarketplaceQ3 2026Browse, share, and sell proven PCB designs. Buy reference designs from experienced engineers, remix them for your project, or list your own designs for the community
AI Auto-Placement EngineQ3 2026RL-based placement with simulated annealing, floorplanning, and per-discipline reward functions
Altium PluginQ3 2026Bring Trace AI into Altium Designer — symbol gen, DRC review, component search without switching tools
Real-time Collaborative EditingQ3 2026Multiple engineers on the same schematic/layout simultaneously, Figma-style cursors and conflict resolution
Cadence Allegro PluginQ4 2026Full bidirectional sync between Allegro and Trace AI
JLCPCB IntegrationQ4 2026Direct ordering, parts library sync, and DFM validation against JLCPCB capabilities
Self-hosted Enterprise DeploymentQ4 2026On-premise backend + model serving for ITAR/classified environments

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Core Design Workflow

When generating bypass capacitor ladders, show the pin number from the datasheet next to each cap so engineers don’t have to search through pages to verify assignments.Status: Requested
When a schematic has many parallel signals (data buses, address buses), automatically convert individual nets to a labeled harness across sheets to reduce visual clutter.Status: Requested
Select a region of the board and run AI-driven placement and routing optimization within that fenced area only. Mirrors how senior designers partition complex boards across specialists.Status: Planned
Specify which schematic sheets the AI should focus on (e.g., “optimize sheets 3-6 for power delivery”) instead of processing the entire schematic.Status: Shipped — Use .tracerules or ask the AI directly: “focus on sheet 3”
Tell the AI what kind of section it’s working on: RF (ground stitching, guarding), power supply (copper pours, via stitching), high-speed digital (length matching, termination), mixed-signal. Different priority weightings per mode.Status: In Progress — Partially supported via .tracerules and natural language prompts. Dedicated modes planned.
Integrate with mechanical CAD (Fusion 360, SolidWorks) so the AI accounts for enclosure constraints — height limits, thermal paths, connector positions, keep-out regions — when placing components.Status: Planned — Q4 2026
Start placement from connector locations and work inward toward the IC, matching how senior engineers actually design boards.Status: In Progress — Supported via natural language (“place connectors first on the edges, then route inward”)
Upload manufacturer reference designs (PDF or image) and have the AI replicate that layout pattern in your design. Particularly valuable for power supplies and RF circuits.Status: In Progress — Datasheet parsing extracts reference circuits. Image-to-layout planned.
When a user adds a chip, automatically pull the manufacturer’s recommended PCB layout, decoupling, and routing specifications from the datasheet and apply them.Status: In Progress — Datasheet parsing + .tracerules handle this partially. Auto-apply planned.
Automatically place AC coupling filters and termination resistors adjacent to their target pins during component placement.Status: Requested — Supported via prompting (“place terminations next to their target pins”). Automated placement engine planned.
Reinforcement learning-based component placement that optimizes for signal integrity, thermal performance, and routability simultaneously.Status: In Progress — Research prototype in development. Simulated annealing + floorplanning pipeline being evaluated.
Start from pre-built circuit templates (USB-C PD, buck converter, STM32 minimal, ESP32 base) and customize from there. Save your own sub-circuits as reusable blocks across projects.Status: Planned
Side-by-side or overlay diff showing what changed between two versions of a schematic — added/removed components, changed connections, moved symbols.Status: Requested
Rename all reference designators matching a pattern, swap all 0603 passives to 0402, change all pull-up values from 10k to 4.7k — in one command.Status: In Progress — Partially supported via Agent mode (“change all 10k pull-ups to 4.7k”). Dedicated batch UI planned.
Automatically add test points on critical nets and fiducials for pick-and-place registration based on manufacturer requirements.Status: Requested
AI-generated pre-fab review checklist covering decoupling, power sequencing, crystal layout, ESD protection, thermal relief, and manufacturing readiness.Status: Requested
Tell the AI “these are my high-speed nets, these are power, these are analog” and it auto-assigns net classes with appropriate width/clearance rules.Status: In Progress — Supported via prompting. Automatic inference from schematic topology planned.

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Routing & Signal Integrity

Route differential pairs (USB, HDMI, Ethernet, PCIe) with automatic length matching, impedance targets, and spacing rules. Visual skew indicator during interactive routing.Status: Shipped — KiCad 10 interactive router supports diff pairs. Improve: AI-assisted constraint setup from interface standard (e.g., “route USB 3.0 per spec”).
Route buses in specific topologies: daisy-chain, star, T-branch, fly-by (DDR). AI selects topology based on the interface standard and suggests optimal routing order.Status: Planned
Interactive length tuning with meander patterns. Set target length, amplitude, and spacing constraints. AI suggests which nets need tuning based on timing requirements.Status: Shipped — Interactive tuning in PCB editor. Improve: AI auto-identifies nets that need length matching from schematic intent.
Visualize signal return paths across reference planes. Flag splits in ground/power planes under high-speed traces. Suggest via stitching to maintain return path continuity.Status: Planned
Cloud autorouter respects controlled impedance requirements — adjusts trace width per layer based on stackup and target impedance.Status: In Progress — Cloud autorouter shipped. Impedance awareness planned.
Minimize via count, avoid via stubs (backdrill suggestions), optimize via placement for signal integrity. Flag unnecessary layer transitions.Status: In Progress — Backdrill support shipped in 1.3.0. AI-driven via optimization planned.
Identify parallel trace segments that may cause crosstalk. Suggest guard traces, spacing increases, or layer reassignment. Pre-route analysis before committing.Status: Planned
Select an interface (DDR4, PCIe Gen4, USB 3.2, HDMI 2.1, 10GbE) and auto-generate all routing constraints: impedance, spacing, length matching, via restrictions, reference planes.Status: Requested
Simulate DC voltage drop and AC impedance across power planes. Identify hot spots, suggest decoupling capacitor values and placement, and validate PDN impedance targets.Status: Planned

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Placement Algorithms

Reinforcement learning agent trained on real PCB designs. Optimizes for routability, signal integrity, thermal distribution, and manufacturing yield simultaneously. Learns from your corrections.Status: In Progress — Simulated annealing + floorplanning pipeline in evaluation. Target: Q3 2026.
Partition the board into functional blocks (power, digital, analog, RF, connectors) before detailed placement. Each block gets its own placement constraints and keep-out boundaries.Status: In Progress
Factor in power dissipation during placement — spread high-power components, place near thermal vias or heatsink mounting points, avoid hot spots under sensitive analog.Status: Planned
After placement, score the result on multiple axes: routability estimate, worst-case trace length, thermal risk, EMC risk. Show engineers exactly where the placement is weak.Status: Requested
Express placement rules in natural language or structured constraints: “USB PHY within 15mm of connector”, “crystal within 5mm of MCU pins 23-24”, “analog section isolated from digital by ground moat”. Engine enforces during optimization.Status: In Progress — Natural language via Agent mode. Structured constraint engine planned.
Generate multiple placement candidates optimizing different tradeoffs (compact vs. thermally relaxed vs. routing-friendly). Engineer picks from the Pareto front.Status: Planned
Auto-detect functional groups from schematic connectivity (power supply block, MCU peripherals, sensor frontend, comms interface) and keep them physically cohesive on the PCB.Status: In Progress — AI infers groups from schematic. Improve: visual group boundaries and locking.

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Symbol & Footprint Generation

When a part isn’t in the KiCad library, generate the symbol automatically from a datasheet or description.Status: Shipped — Works for most ICs. Improve: scale to high-pin-count parts (900+ pins currently unreliable).
For very large ICs (900+ pins), break the symbol into logical sub-blocks (gates, power, JTAG, etc.) automatically.Status: In Progress
Ensure all generated symbols pass IPC compliance checks before being added to the design.Status: Shipped — Improve: relax over-strict validation on complex ICs that blocks valid generations.
Auto-generate footprints from manufacturer datasheets when not in the standard library.Status: Shipped — Improve: support more package types and land pattern variants.
Import component libraries from Altium, KiCad, Cadence and export Trace’s libraries to other formats.Status: Shipped — KiCad native. Altium and Cadence import via EDA importers.
Show NAND, OR, AND gates in their traditional shapes for analog engineers, not as rectangular boxes.Status: Shipped — Inherited from KiCad 10. IEEE and IEC symbol styles available in Preferences.

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Manufacturing & Fabrication

Automatically arrange multiple boards on a fabrication panel with configurable mouse bites, V-scoring, breakaway tabs, and inset/offset arrangements.Status: Planned
Get instant quotes from multiple manufacturers (PCBWay, Pikkolo, JLCPCB, OSH Park) inline so users can compare pricing without leaving Trace.Status: In Progress — PCBWay and Pikkolo live. Additional fabs planned.
Pull DRC rules from each manufacturer’s API so designs validate against the specific fab’s capabilities.Status: Shipped — See manufacturer DRC presets. Improve: add more manufacturer presets.
Validate designs against assembly capabilities — component density, double-sided assembly, pick-and-place tolerances — separately from DFM.Status: Planned
Specify layer count, copper weight, dielectric thickness, controlled impedance requirements, and have the AI place/route accordingly.Status: Shipped — Board Setup → Stackup. Improve: AI should auto-suggest stackup from signal requirements.
Filter component selection by grade: defense/MIL-SPEC, automotive (AEC-Q100), rad-hardened, or commercial-only.Status: Requested — Partially supported via .tracerules (“only use automotive-grade components”).
When DFM fails (clearance too small, annular ring too tight, drill size wrong), the AI proposes fixes automatically.Status: In Progress — AI offers to fix common violations after DRC runs. Improve: expand coverage.
Let enterprise customers add their internal fabrication capabilities or preferred manufacturers via API.Status: Planned — Enterprise tier
Web-based BOM viewer with click-to-highlight on the PCB render. Share with teammates for review without needing Trace installed.Status: Planned
Show component placement order and rotation on the PCB for assembly verification before sending to fab.Status: Requested
Design multiple interconnected PCBs in a single project — define board-to-board connectors and validate inter-board signals.Status: Planned

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Component Sourcing

DigiKey, Mouser, Arrow, LCSC, JLCPCB integrated and visible at the BOM level.Status: Shipped — Improve: deeper inline BOM integration with quantity-based pricing.
Surface expected delivery time for each component on the BOM, especially for parts with 26+ week lead times.Status: Requested
When a part is out of stock, suggest pin-compatible or footprint-compatible alternatives.Status: Shipped — Improve: better parametric matching and explicit “swap” workflow.
For enterprise customers, integrate with the customer’s internal stockroom so designs prefer in-house parts.Status: Planned — Enterprise tier
Alert when a chosen part is end-of-life, NRND, or being phased out.Status: In Progress — Partial via Nexar data. Improve: proactive alerts in BOM view.
Validate that every manufacturer part number on the BOM is real, current, and orderable before submission.Status: Shipped — Improve: deeper validation against distributor APIs with stock-level confidence.
Given a target budget, suggest alternative components that meet specs but reduce total BOM cost. Factor in quantity breaks and distributor pricing tiers.Status: Requested

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AI / ML Capabilities

Define persistent rules that shape how the AI designs your circuits. Component preferences, layout conventions, manufacturing targets.Status: Shipped (Beta) — See .tracerules documentation.
The model learns each engineer’s correction patterns over time so outputs adapt to individual style.Status: In Progress — .tracerules is the manual version. Learned personalization planned.
Agent learns from corrections in a simulated environment with reward functions tuned per discipline.Status: In Progress
Describe placement rules in plain English. LLM parses to JSON for the placement engine.Status: Shipped — “Keep the regulator 10mm from the MCU” works today in Agent mode.
Train custom model variants on a customer’s specific design history and constraints.Status: Planned — Enterprise tier
Visible AI reasoning process with 10K-token thinking budget per step.Status: Shipped
Try different design approaches in parallel without losing history. Fork a conversation, explore option A and option B, then merge the winner back.Status: Requested
AI-driven SI checks: impedance matching, crosstalk estimation, return path analysis. Integrates with IBIS models when available.Status: Planned
Heat map visualization showing power dissipation, thermal via recommendations, and copper pour optimization for heat spreading.Status: Planned
Voltage drop analysis, current density visualization, and power plane integrity checks.Status: Planned
Basic electromagnetic compatibility checks before lab testing — loop area analysis, decoupling effectiveness, ground plane continuity.Status: Planned

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Collaboration & Teams

Multiple engineers working on the same design with role-based access, version control, and design history.Status: In Progress — Team billing and invites shipped. Shared workspaces planned.
Enterprise single sign-on for org-level access management.Status: Planned — Enterprise tier
Track every action on a design: who placed what, who routed what, who edited what.Status: Planned — Enterprise tier
Multiple engineers working on the same schematic or layout simultaneously.Status: Planned
Leave notes on specific components, traces, or sections during review.Status: Requested
Share read-only access with external advisors for feedback without giving full edit rights.Status: Requested
Formal review process: submit design for review → reviewers annotate → approve/reject with comments → iterate. Audit trail for each review cycle.Status: Planned
Engineering Change Orders tracked through Trace: what changed, who approved it, what’s the impact on BOM/fab/assembly. Links to specific schematic/layout versions.Status: Planned — Enterprise tier
Transfer a project between engineering teams (e.g., concept team → production team) with full history, design intent, and constraints preserved.Status: Requested

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Security & Compliance

For ITAR-restricted, classified, or defense-sensitive work where IP cannot leave the customer’s environment.Status: Planned — Enterprise tier
Design files live on your machine. The AI assists via streaming connection but files never leave your control.Status: Shipped — This is how Trace works by default. See How Trace Works.
Contractual guarantee that customer designs aren’t used to train Trace’s models.Status: Shipped — In our Terms of Service. Enterprise customers get additional contractual protections.
Status: In Progress — Target Q3 2026
For defense contractors handling export-controlled designs.Status: Planned — Enterprise tier, requires self-hosted deployment
Fully offline operation with local model inference (no internet required). For SCIFs, classified environments, and locations without connectivity.Status: Planned — Enterprise tier
Invisible watermarks embedded in Gerber/ODB++ output that trace back to the originating engineer and organization. Detects unauthorized distribution of manufacturing files.Status: Requested
Fine-grained permissions: viewer, editor, reviewer, admin. Control who can edit schematics, approve plans, submit to manufacturing, or access sensitive projects.Status: Planned — Enterprise tier
Choose where your data is stored (US, EU, APAC). Required for GDPR, data sovereignty, and certain government contracts.Status: Planned — Enterprise tier

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Plugin Architecture

Bring Trace AI capabilities into Altium Designer without forcing engineers to switch tools.Status: Planned
Status: Shipped — Trace is built on KiCad. Full native integration.
Status: Planned
Status: Planned
Status: Planned
Move designs between Trace native and any plugin-enabled tool with full fidelity.Status: In Progress — Altium, Cadence Allegro, Mentor PADS, and gEDA import supported via EDA Importers.

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Documentation & Outputs

Schematic exports, BOM PDFs, assembly drawings, fab notes generated automatically.Status: Shipped — BOM, Gerber, drill, pick-and-place, PDF plots. Improve: assembly drawings.
Status: Shipped — Gerber and IPC-2581 supported. ODB++ planned.
Export the populated PCB as a 3D model for mechanical integration / enclosure design.Status: Shipped — STEP and VRML export from 3D Viewer.
Generate visualization of the finished board for marketing or customer-facing materials.Status: Shipped — 3D Viewer with raytracing. Improve: one-click export workflow.
Generate separate BOMs per design variant — different component populations for different product SKUs.Status: Shipped — Design variants support variant-aware exports. See Design Variants.
Auto-generate documentation packages for FDA (medical), FAA (aerospace), FCC (consumer electronics) submissions.Status: Planned
Track every component back to its source manufacturer and distributor lot for compliance audits.Status: Planned — Enterprise / defense tier

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Workflow & UX

Pause the AI mid-generation to change parameters, flip a component, change material, then continue from there.Status: Shipped — Plan mode supports approve, adjust, or reject at each step.
Tell the AI to iterate extensively on the plan before touching any files. Go through multiple rounds of research, refinement, and validation before a single component is placed. For complex or high-stakes designs where you want the AI to think 10x before acting.Status: In Progress — Plan mode supports research + questions + approval. Improve: configurable iteration depth (“iterate 5 times on this plan before executing”), automatic re-evaluation loops, and explicit “don’t touch files until I say go” constraint.
Status: Shipped — All three platforms supported as of v1.3.0.
Status: Shipped — Dashboard supports dark mode. Desktop app uses system theme.
Let users remap shortcuts to match their muscle memory from Altium / KiCad / Cadence.Status: Shipped — Preferences → Hotkeys. Full remapping supported.
Review designs on the go without full editing.Status: Requested
Built-in stackup-aware impedance calculator for controlled impedance routing — microstrip, stripline, differential pairs.Status: Shipped — PCB Calculator app included with Trace. Improve: integrate directly into Board Setup.
Click a component in the schematic → instantly highlight and zoom to it on the PCB (and vice versa). AI-aware cross-probing that explains the connection context.Status: Shipped — Basic cross-probe works. Improve: AI-enhanced context (“this is the feedback resistor for U3’s output stage”).

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Developer Tools

Command-line interface for power users and CI/CD pipelines.Status: Shipped — See CLI documentation and CLI commands.
Run Trace operations programmatically without the GUI for automation.Status: In Progress
Fire events when designs reach key states (validation complete, ordered, manufactured).Status: Planned
Let teams build custom workflows, dashboards, or integrations on top of Trace.Status: In Progress — Chat, downloads, auth, and manufacturer APIs available. Expanding.
Design status updates and manufacturing alerts pushed to team channels.Status: Planned
Version control for hardware designs through Git.Status: Shipped — Local history uses git. Improve: remote repo push/pull.

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Education & Onboarding

Guided walkthroughs for new engineers learning hardware design.Status: In Progress
Partner with universities to offer Trace as part of EE education.Status: In Progress — See Education Program.
Extra guardrails and explanations for engineers under 5 years of experience.Status: Requested — Partially addressed via Ask mode’s explanatory responses.

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Integration & API

Track PCB design tasks alongside firmware/software issues in the same project tracker.Status: Planned
Enterprise customers add their internal fab capabilities via API.Status: Planned — Enterprise tier

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Known Issues Being Addressed

IssueStatus
High-pin-count symbol generation (900+ pins)In progress — multi-unit decomposition
Plan mode timeout on large schematicsFixed in 1.3.0 (extended timeouts + progress reporting)
Windows refocus bug (AI steals window focus)Fixed in 1.3.0
Token efficiency on broad queriesImproved in 1.3.0 (better context scoping)
PCBWay ConfirmOrder API failuresFixed in 1.3.0
Schematic title persists when starting a new chatInvestigating — AI inherits context from the project title which can bias new conversations
This list is community-driven and updated regularly. Features are prioritized by user votes, beta tester feedback, strategic alignment, and engineering feasibility. Timelines are estimates, not commitments.

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How Requests Get Prioritized

  1. Vote on Discord — Requests with the most upvotes in #feature-requests get reviewed first
  2. Beta feedback — Active beta testers who report bugs and test features get their requests fast-tracked
  3. Design partner calls — Engineers who join advisory calls provide direct input on priorities
  4. Strategic alignment — Some features unlock entire categories of users or markets

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Join the Beta

The fastest way to influence what gets built: apply for the beta program. You get:
  • Free Trace access (all AI modes, no subscription needed)
  • Direct line to the engineering team
  • Your bugs and requests prioritized
  • Points for feedback, redeemable for swag and extended access
Apply from your dashboard.

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Community-Derived Requests

Extracted from Discord conversations, Twitter discussions, and user feedback sessions.
Configurable symbol rendering per project — US-style resistors (zigzag) vs EU-style (rectangle), ground symbols, etc. Engineers working across regions or for international clients need to switch seamlessly.Status: Shipped — KiCad 10 supports both IEEE and IEC styles in Preferences. Improve: per-project style lock via .tracerules so AI generates consistent symbols.
Upload or open a schematic and get detailed design review feedback: wake-up pin selection, I2C address flexibility (pull-up/down options), spare IO breakout to headers, connector standard recommendations (STEMMA/QWIIC), LED current optimization, and power path alternatives.Status: In Progress — Ask mode provides general review. Improve: structured checklist output with specific pin/component recommendations.
Built-in calculator for LED series resistor values, forward voltage lookup, and current limiting. Support for RGB LEDs, low-current alternatives, and brightness matching.Status: Requested — Partially supported via Ask mode. Dedicated inline calculator planned.
AI recommends power path management approaches: ideal diodes (TI LM66200), eFuses, load switches, OR-ing controllers based on the design’s power requirements, battery chemistry, and fault protection needs.Status: In Progress — Supported via Ask mode and parts search. Improve: proactive suggestions when power input topology is detected.
When adding an I2C device, suggest pull-up/pull-down resistor options for address pins to enable flexibility. Flag potential address conflicts when multiple I2C devices share a bus.Status: Requested
Given requirements (pin count, current, stack height, cost target, assembly method), recommend the best connector family: mezzanine B2B, FFC, card edge, JST SH/STEMMA, or 2.54mm headers. Factor in assembly difficulty and failure modes.Status: Planned
Auto-generate STEP files from package dimensions in a datasheet. No more hunting for 3D models or manually creating them in FreeCAD for every non-standard part.Status: Planned
Detect designs intended for harsh environments (outdoor, water-adjacent, high-vibration) and suggest conformal coating, potting, strain relief, and mechanical fastening beyond just solder joints.Status: Requested
When a design uses RF (WiFi, BLE, LoRa), provide compliance guidance: FCC 15b (unintentional radiator) for the PCB, FCC 15c (intentional radiator) for custom RF, and when pre-certified modules eliminate the need for full testing.Status: Requested — Partially covered in Ask mode for general questions.
Support designs where a primary MCU (ESP32) programs secondary MCUs (ATtiny, RP2040, PSoC) via UART/SPI during boot. Help with ISP pin routing, boot mode selection, and firmware partition planning.Status: Requested
When assigning MCU pins, prioritize wake-up capable pins for interrupt inputs, ensure boot/ISP pins aren’t conflicting, and flag when high-speed peripherals are assigned to non-optimal pins.Status: In Progress — Signal path tracing helps. Improve: explicit pin capability awareness from MCU datasheets.
When a design uses multiple discrete logic gates or 555 timers, suggest compact programmable logic alternatives like Renesas GreenPAK or small CPLDs that reduce BOM count and board space.Status: Requested
When routing tight-pitch components (BGA, QFN) or high-speed USB/HDMI, proactively suggest via-in-pad with backfill, and flag the additional manufacturing cost.Status: Requested — Supported via prompting. Automatic detection planned.
Support fabs beyond China and US: PCBPower (India), Eurocircuits (EU), Würth (Germany), local shops. Engineers choose local for communication, lead time, and avoiding import duties.Status: Planned — PCBWay and Pikkolo shipped. More fabs coming.
Import SVG logos, mascots, and artistic silkscreen designs with proper conversion to copper/silkscreen layers. One-click import that handles DRC-safe minimum line widths.Status: Shipped — KiCad supports SVG import to silkscreen. Improve: AI-assisted placement and DRC-safe scaling.
Templates for common interfaces: LoRa + GPS tracker, USB-C PD sink, CAN bus node, BLE beacon, ESP32 base station, RP2040 minimal. Pre-validated schematics with correct antenna matching, decoupling, and crystal placement.Status: Planned — Partially available via Ask mode reference suggestions.
Pi-filter value calculation from NanoVNA measurements or target impedance. Smith chart visualization, matching network topology selection (L, Pi, T), and component value optimization with standard E-series values.Status: Planned
For high-power components (voltage regulators, FETs, LEDs), auto-generate thermal via arrays under exposed pads with configurable pitch, drill size, and connection to internal copper pours.Status: Requested
Show running total BOM cost as you add components, with quantity-break pricing visible. Alert when a component pushes the total beyond a target budget.Status: Requested
Given board dimensions and fab minimum panel size, calculate optimal panelization (1x2, 2x2, 1x3) to minimize waste and cost. Account for JLC/PCBWay panel constraints and rail requirements.Status: Planned
Curated, proven open-source reference designs: Bitcoin miner boards, VR trackers, IoT sensors, motor controllers, drone flight controllers. Fork and customize instead of starting from scratch.Status: Planned — See PCB Marketplace (Coming Soon).
Guided onboarding for software developers transitioning to hardware: start with basic circuits (LED + resistor), progress through power supplies, MCU breakouts, and multi-layer designs. Progress tracking, achievements, and community challenges.Status: In Progress — See Education Program. Improve: in-app guided progression.
For hobbyist/prototype boards: suggest component placement order for hand soldering (smallest first, heat-sensitive last), generate a visual assembly guide with numbered steps, and flag components that require reflow.Status: Requested
Gallery of real boards designed and manufactured through Trace. Filterable by complexity, use case, and components used. Engineers can share their work and inspire others.Status: In Progress — Discord showcase channel active. In-platform gallery planned.
Connect PCB designers with companies needing custom boards. Skill verification, portfolio showcase, escrow payments, and NDA management. Bridge the gap between experienced designers and companies with hardware needs.Status: Planned — See PCB Marketplace (Coming Soon).
Upload X-ray images of assembled boards and get AI-assisted defect detection: tombstoning, bridging, cold joints, missing components, BGA voiding.Status: Planned
Auto-modify stencil apertures based on component type: reduce for fine-pitch QFP to prevent bridging, enlarge for thermal pads, add home-plate shapes for BGA. Export optimized stencil Gerber separately.Status: Requested
Design board-to-board and board-to-external cable harnesses: connector pinout mapping, wire gauge selection, crimp terminal specification, and IDC cable generation. Export cable assembly drawings.Status: Planned
When using an MCU with Zephyr support, auto-generate devicetree pin mappings from the schematic. Ensure pin assignments are compatible with Zephyr driver requirements.Status: Requested
Estimate total power consumption from BOM — pull sleep/active current from datasheets, calculate battery life for different duty cycles, and flag components with high quiescent current that break a power budget.Status: Requested
From an MCU schematic, auto-generate a breakout board: route all unused GPIO to standard 2.54mm headers, add STEMMA/QWIIC connector for I2C, expose SWD/JTAG, and include USB-C for power/programming.Status: Requested
Flag components that can’t be hand-assembled (BGA, 0201, QFN with exposed pad) and score the board’s overall assembly difficulty. Suggest alternatives when targeting home/prototype assembly.Status: Requested
When mixing voltage domains (3.3V MCU to 5V/12V legacy IO), auto-suggest level translators, voltage dividers, or open-drain configurations based on signal direction and speed requirements.Status: In Progress — Supported via Ask mode. Automatic detection of voltage domain mismatches planned.
When a target PNP machine or panel constraint is specified (e.g., 220mm max conveyor width), enforce board outline limits during design and suggest panelization that fits.Status: Requested
When adding I2C/SPI/UART expansion, suggest standard pinout conventions (STEMMA/QWIIC for I2C, Pmod for SPI) so boards are compatible with the broader ecosystem of breakout modules.Status: Requested
Based on connector types and pad requirements (card edge needs gold fingers, fine-pitch BGA needs ENIG, hobby boards can use HASL), suggest the optimal surface finish and flag cost implications.Status: Requested
Given component count, pad pitch, and assembly method, estimate first-pass yield and rework rate. Help engineers understand the manufacturing risk of their design complexity.Status: Planned
Show side-by-side pricing from JLC, PCBWay, Pikkolo, OSH Park, and local fabs for the current board — including shipping, assembly, and lead time. Engineers currently get quotes one-at-a-time.Status: In Progress — PCBWay and Pikkolo quotes live. Multi-fab comparison view planned.
Analyze connector choices and component mounting for shock/vibration environments. Flag 2.54mm headers that disconnect on drop tests, suggest locking connectors, and recommend reinforcement strategies.Status: Requested
Import EasyEDA / LCEDA projects directly into Trace with full symbol, footprint, and routing preservation. Many engineers start in EasyEDA for JLC integration and want to migrate to a more capable tool.Status: Planned
For RP2040 PIO, ESP32 RMT, and similar programmable peripherals, generate configuration code from timing diagrams or protocol descriptions. Bridges the gap between hardware routing and firmware initialization.Status: Requested
Given two PCBs that need to connect, compare options (FFC, B2B mezzanine, card edge, wire harness, castellated edge) across cost, pin count, reliability, insertion cycles, and assembly difficulty.Status: Requested
Community competitions with specific constraints (smallest board, lowest BOM cost, most creative silkscreen, fastest route). Builds engagement and provides real-world practice for learners.Status: Planned
Share PCB designs publicly without revealing your real identity. Engineers at companies with strict IP policies want to showcase personal work without linking to their employer’s GitHub.Status: Requested
End-to-end guide: stencil ordering, paste application, PNP programming (NeoDen K8, LumenPnP), reflow profile setup, and through-hole selective soldering. Trace exports optimized for each step.Status: Requested
Design modules with castellated edges for board-to-board soldering. Auto-generate the half-via edge pattern, test points, and pick-and-place compatible panels.Status: Shipped — KiCad supports castellated pads. Improve: AI-assisted module breakout with auto-generated carrier board.
Templates for IMU + gyro + magnetometer boards with Kalman filter firmware scaffolding. Pre-validated layouts for BMI270, ICM-42688, BMM350 with correct decoupling, mounting orientation markers, and CAN/SPI output.Status: Requested
Upload a logo image and auto-convert to DRC-safe silkscreen or copper artwork. Handle minimum line widths, simplify complex vectors, and preview at fabrication resolution. No more hours in Inkscape.Status: Requested
Manage thousands of components with lifecycle status, preferred suppliers, company-specific metadata. Altium-style database library without the Altium price tag. Team-shared with version control.Status: Planned
Visualize return paths, flag ground plane splits under high-speed traces, and identify areas where via stitching is needed. Color-code ground plane connectivity per net.Status: Planned
When designing multi-PCB stacks, calculate total height from PCB thickness + component height + connector mating height. Flag interference with enclosure constraints.Status: Requested
For assembled boards needing fixes, generate step-by-step rework procedures: required tools, temperature profiles, component removal sequence, and re-soldering guidance for specific package types.Status: Requested
Given a PNP machine’s feeder capacity (e.g., 66 slots at 8mm, fewer for wide components), plan which components go in feeders vs IC trays, and suggest BOM optimizations to fit within machine constraints.Status: Requested
For combined LoRa/BLE + GNSS boards, guide antenna placement: ground plane keep-outs, separation distance, matching network layout, and coexistence best practices for RAK, Quectel, u-blox modules.Status: Requested
Templates for modular systems: DIN rail, 19” rack, Eurocard form factors with standard connector positions, front panel design, and backplane interconnect planning.Status: Requested
Pre-validated circuits for H-bridge, half-bridge, ideal diode ORing, hot-swap, inrush limiting, and reverse polarity protection. Sized for common voltage/current ranges with FET selection guidance.Status: Requested
Given a target BOM cost, suggest the cheapest working solution for each functional block. “I need a voltage regulator, JLCPCB-stocked, under $0.10” → ranked suggestions with tradeoff notes.Status: In Progress — Parts search shows pricing. Improve: explicit budget constraint mode.
For home prototyping with CNC routers: enforce minimum trace widths for milling, single/double layer only, avoid features requiring chemistry (plated vias), and generate isolation routing G-code.Status: Requested
Constraints for wearable electronics: max board dimensions, flex PCB support, battery placement optimization, low-profile component enforcement, and weight estimation.Status: Requested
Solar MPPT, piezo harvesting, thermal (TEG) circuits with ultra-low-power management ICs (BQ25570, SPV1050). Pre-validated for common panel sizes and indoor/outdoor light levels.Status: Requested
For each critical component, auto-suggest 2-3 pin/footprint-compatible alternatives from different manufacturers. Generate a “plan B” BOM that can be swapped without board respin.Status: In Progress — Alternative part suggestions exist. Improve: explicit second-source BOM column.
Show both naming conventions inline: 0402 (imperial) = 1005 (metric). Auto-convert based on user preference. Eliminate confusion when datasheets and fab houses use different systems.Status: Requested
Given a BOM (component list with values and package sizes), generate a plausible schematic interconnection. For cases where a client provides parts but no design — the AI infers the circuit topology.Status: Planned
Import mechanical board outlines from DXF/STEP with automatic keep-out region detection (mounting holes, connector cutouts, height restrictions) and snap to grid.Status: Shipped — KiCad supports DXF import. Improve: auto-detect keep-outs from mechanical model features.
Pre-validated circuits for driving 7-segment displays, LED matrices, NeoPixel/WS2812 strips, and OLED modules. Include shift register cascading, PWM driver selection, and current budgeting.Status: Requested
Auto-add SWD/JTAG headers, UART debug ports, serial MUX for multi-MCU ISP, and test points on critical signals. Configurable between “full debug” (development) and “minimal” (production) variants.Status: In Progress — Partially via Agent mode. Dedicated debug infrastructure tool planned.
Select PoE class (802.3af/at/bt), configure PD interface IC, isolation transformer, and DCDC converter. Auto-generate the compliant circuit with proper thermal derating for the chosen wattage.Status: Requested
Pre-configured for harsh environments: automotive temp ranges (-40 to +125C), AEC-Q100 component filtering, CAN/LIN bus circuits, and DO-254 documentation scaffolding for avionics.Status: Planned
Live circuit simulation with draggable parameter sliders, virtual oscilloscopes, voltage/current sources, and probes. Tweak a resistor value and see the output waveform change in real-time. A digital breadboard that makes analog design intuitive — especially for students learning op-amp configurations, filters, and power supplies.Status: Planned — Transformative for education and rapid prototyping. Research phase.
AI-assisted fan-out from dense BGA packages. Learn escape patterns from manufacturer reference designs (Xilinx, NXP, TI) and generate layer-by-layer breakout routing with proper via transitions and impedance continuity.Status: Planned
Connect open-source instruments (Saleae, DSLogic, Analog Discovery) to test points on your board. Ask “my SPI looks wrong, what’s happening?” and Trace captures signals, decodes protocols, and diagnoses issues using the schematic as context.Status: Planned
Generate purpose-built firmware to exercise specific signals for board bring-up: toggle GPIOs, generate SPI/I2C traffic, sweep DAC outputs, measure ADC inputs. Flash it, verify hardware, then load production firmware.Status: Requested
Support FPGA-based designs: pin planning with constraint file generation, clock domain visualization, block RAM inference, and MCP bridge to Vivado/Yosys for synthesis feedback. Target both commercial (Xilinx/AMD) and open-source (iCE40, ECP5) toolchains.Status: Planned
Point to a chip datasheet and auto-extract the recommended application circuit — all supporting components (decoupling caps, crystal, pull-ups, boot resistors, programming header) added in one shot. Learn from TI, STMicro, NXP reference designs.Status: In Progress — Datasheet parsing extracts circuits. Auto-import to schematic planned.
Flag circuit mistakes that require domain knowledge: driving MOSFETs in linear region from weak GPIO, missing gate drivers, incorrect bias networks, capacitive loading on high-impedance nodes, ground loops in mixed-signal designs.Status: In Progress — ERC catches basic errors. AI-powered topology-aware detection planned.
Support intentionally empty footprints for debug/production variants: optional pull-ups, alternative filter values, test points, jumper resistors. Track which slots are intentional vs accidentally missing.Status: Shipped — KiCad supports DNP (Do Not Populate) marking. Improve: AI suggests where flexibility slots would be valuable.