> ## Documentation Index
> Fetch the complete documentation index at: https://docs.buildwithtrace.com/llms.txt
> Use this file to discover all available pages before exploring further.

# Feature Requests

> Community-driven feature requests for Trace. Submit requests, track what's being built, and get early access through the beta program.

<Info>
  This is a living document. Features are prioritized by community demand, beta tester feedback, and strategic alignment.
</Info>

## Submit a Request

<CardGroup cols={3}>
  <Card title="Discord" icon="discord" href="https://discord.gg/UNUvQxneCr">
    Post in **#feature-requests** and upvote others' ideas
  </Card>

  <Card title="Email" icon="envelope" href="mailto:hello@buildwithtrace.com">
    [hello@buildwithtrace.com](mailto:hello@buildwithtrace.com)
  </Card>

  <Card title="Beta Feedback" icon="flask" href="https://buildwithtrace.com/dashboard/beta/feedback">
    Submit from the dashboard (earns points)
  </Card>
</CardGroup>

<Tip>
  **Want your request prioritized?** [Join the beta program](/resources/beta) — beta members get free Trace access in exchange for active feedback. Engineers who test features and report issues get their requests fast-tracked.
</Tip>

Legend: <span style={{color: '#16a34a'}}>**Shipped**</span> · <span style={{color: '#ca8a04'}}>**In Progress**</span> · <span style={{color: '#6366f1'}}>**Planned**</span> · <span style={{color: '#6b7280'}}>**Requested**</span>

***

## Coming Soon

Features currently in active development with target release windows:

| Feature                               | Target  | Description                                                                                                                                                           |
| ------------------------------------- | ------- | --------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
| **PCB Marketplace**                   | Q3 2026 | Browse, share, and sell proven PCB designs. Buy reference designs from experienced engineers, remix them for your project, or list your own designs for the community |
| **AI Auto-Placement Engine**          | Q3 2026 | RL-based placement with simulated annealing, floorplanning, and per-discipline reward functions                                                                       |
| **Altium Plugin**                     | Q3 2026 | Bring Trace AI into Altium Designer — symbol gen, DRC review, component search without switching tools                                                                |
| **Real-time Collaborative Editing**   | Q3 2026 | Multiple engineers on the same schematic/layout simultaneously, Figma-style cursors and conflict resolution                                                           |
| **Cadence Allegro Plugin**            | Q4 2026 | Full bidirectional sync between Allegro and Trace AI                                                                                                                  |
| **JLCPCB Integration**                | Q4 2026 | Direct ordering, parts library sync, and DFM validation against JLCPCB capabilities                                                                                   |
| **Self-hosted Enterprise Deployment** | Q4 2026 | On-premise backend + model serving for ITAR/classified environments                                                                                                   |

***

## Core Design Workflow

<AccordionGroup>
  <Accordion title="Cap pin reference labels in schematic generation">
    When generating bypass capacitor ladders, show the pin number from the datasheet next to each cap so engineers don't have to search through pages to verify assignments.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Bus / harness routing for complex schematics">
    When a schematic has many parallel signals (data buses, address buses), automatically convert individual nets to a labeled harness across sheets to reduce visual clutter.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Fence-based section optimization">
    Select a region of the board and run AI-driven placement and routing optimization within that fenced area only. Mirrors how senior designers partition complex boards across specialists.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Sheet-based scope selection">
    Specify which schematic sheets the AI should focus on (e.g., "optimize sheets 3-6 for power delivery") instead of processing the entire schematic.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — Use [.tracerules](/concepts/tracerules) or ask the AI directly: "focus on sheet 3"
  </Accordion>

  <Accordion title="Discipline-aware optimization modes">
    Tell the AI what kind of section it's working on: RF (ground stitching, guarding), power supply (copper pours, via stitching), high-speed digital (length matching, termination), mixed-signal. Different priority weightings per mode.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — Partially supported via [.tracerules](/concepts/tracerules) and natural language prompts. Dedicated modes planned.
  </Accordion>

  <Accordion title="Mechanical-PCB co-design">
    Integrate with mechanical CAD (Fusion 360, SolidWorks) so the AI accounts for enclosure constraints — height limits, thermal paths, connector positions, keep-out regions — when placing components.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span> — Q4 2026
  </Accordion>

  <Accordion title="Connector-first placement">
    Start placement from connector locations and work inward toward the IC, matching how senior engineers actually design boards.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — Supported via natural language ("place connectors first on the edges, then route inward")
  </Accordion>

  <Accordion title="Reference design ingestion from datasheets">
    Upload manufacturer reference designs (PDF or image) and have the AI replicate that layout pattern in your design. Particularly valuable for power supplies and RF circuits.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — Datasheet parsing extracts reference circuits. Image-to-layout planned.
  </Accordion>

  <Accordion title="Manufacturer layout recommendations">
    When a user adds a chip, automatically pull the manufacturer's recommended PCB layout, decoupling, and routing specifications from the datasheet and apply them.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — Datasheet parsing + [.tracerules](/concepts/tracerules) handle this partially. Auto-apply planned.
  </Accordion>

  <Accordion title="AC coupling filter and termination placement">
    Automatically place AC coupling filters and termination resistors adjacent to their target pins during component placement.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span> — Supported via prompting ("place terminations next to their target pins"). Automated placement engine planned.
  </Accordion>

  <Accordion title="AI-driven auto-placement">
    Reinforcement learning-based component placement that optimizes for signal integrity, thermal performance, and routability simultaneously.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — Research prototype in development. Simulated annealing + floorplanning pipeline being evaluated.
  </Accordion>

  <Accordion title="Design templates and reusable blocks">
    Start from pre-built circuit templates (USB-C PD, buck converter, STM32 minimal, ESP32 base) and customize from there. Save your own sub-circuits as reusable blocks across projects.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Visual diff between schematic versions">
    Side-by-side or overlay diff showing what changed between two versions of a schematic — added/removed components, changed connections, moved symbols.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Batch operations">
    Rename all reference designators matching a pattern, swap all 0603 passives to 0402, change all pull-up values from 10k to 4.7k — in one command.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — Partially supported via Agent mode ("change all 10k pull-ups to 4.7k"). Dedicated batch UI planned.
  </Accordion>

  <Accordion title="Test point and fiducial auto-placement">
    Automatically add test points on critical nets and fiducials for pick-and-place registration based on manufacturer requirements.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Design review checklist">
    AI-generated pre-fab review checklist covering decoupling, power sequencing, crystal layout, ESD protection, thermal relief, and manufacturing readiness.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Net class management via AI">
    Tell the AI "these are my high-speed nets, these are power, these are analog" and it auto-assigns net classes with appropriate width/clearance rules.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — Supported via prompting. Automatic inference from schematic topology planned.
  </Accordion>
</AccordionGroup>

***

## Routing & Signal Integrity

<AccordionGroup>
  <Accordion title="Length-matched differential pair routing">
    Route differential pairs (USB, HDMI, Ethernet, PCIe) with automatic length matching, impedance targets, and spacing rules. Visual skew indicator during interactive routing.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — KiCad 10 interactive router supports diff pairs. Improve: AI-assisted constraint setup from interface standard (e.g., "route USB 3.0 per spec").
  </Accordion>

  <Accordion title="Topology-aware routing">
    Route buses in specific topologies: daisy-chain, star, T-branch, fly-by (DDR). AI selects topology based on the interface standard and suggests optimal routing order.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Meander / trombone tuning">
    Interactive length tuning with meander patterns. Set target length, amplitude, and spacing constraints. AI suggests which nets need tuning based on timing requirements.

    **Status:** <span style={{color: '#16a34a'}}>Shipped (Alpha)</span> — Interactive tuning in PCB editor, plus [Matched Length Groups](/concepts/pcb-layout#matched-length-groups) for length-matching a whole bus to a shared target (incl. nets split by series resistors). Improve: AI auto-identifies nets that need length matching from schematic intent.
  </Accordion>

  <Accordion title="Return path analysis">
    Visualize signal return paths across reference planes. Flag splits in ground/power planes under high-speed traces. Suggest via stitching to maintain return path continuity.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Impedance-aware autorouting">
    Cloud autorouter respects controlled impedance requirements — adjusts trace width per layer based on stackup and target impedance.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — Cloud autorouter shipped. Impedance awareness planned.
  </Accordion>

  <Accordion title="Via optimization">
    Minimize via count, avoid via stubs (backdrill suggestions), optimize via placement for signal integrity. Flag unnecessary layer transitions.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — Backdrill support shipped in 1.3.0. AI-driven via optimization planned.
  </Accordion>

  <Accordion title="Crosstalk estimation">
    Identify parallel trace segments that may cause crosstalk. Suggest guard traces, spacing increases, or layer reassignment. Pre-route analysis before committing.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="High-speed design rule wizard">
    Select an interface (DDR4, PCIe Gen4, USB 3.2, HDMI 2.1, 10GbE) and auto-generate all routing constraints: impedance, spacing, length matching, via restrictions, reference planes.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Power delivery network (PDN) analysis">
    Simulate DC voltage drop and AC impedance across power planes. Identify hot spots, suggest decoupling capacitor values and placement, and validate PDN impedance targets.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>
</AccordionGroup>

***

## Placement Algorithms

<AccordionGroup>
  <Accordion title="AI auto-placement with RL">
    Reinforcement learning agent trained on real PCB designs. Optimizes for routability, signal integrity, thermal distribution, and manufacturing yield simultaneously. Learns from your corrections.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — Simulated annealing + floorplanning pipeline in evaluation. Target: Q3 2026.
  </Accordion>

  <Accordion title="Hierarchical floorplanning">
    Partition the board into functional blocks (power, digital, analog, RF, connectors) before detailed placement. Each block gets its own placement constraints and keep-out boundaries.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span>
  </Accordion>

  <Accordion title="Thermal-aware placement">
    Factor in power dissipation during placement — spread high-power components, place near thermal vias or heatsink mounting points, avoid hot spots under sensitive analog.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Placement scoring and feedback">
    After placement, score the result on multiple axes: routability estimate, worst-case trace length, thermal risk, EMC risk. Show engineers exactly where the placement is weak.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Constraint-driven placement">
    Express placement rules in natural language or structured constraints: "USB PHY within 15mm of connector", "crystal within 5mm of MCU pins 23-24", "analog section isolated from digital by ground moat". Engine enforces during optimization.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — Natural language via Agent mode. Structured constraint engine planned.
  </Accordion>

  <Accordion title="Multi-objective Pareto optimization">
    Generate multiple placement candidates optimizing different tradeoffs (compact vs. thermally relaxed vs. routing-friendly). Engineer picks from the Pareto front.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Component grouping intelligence">
    Auto-detect functional groups from schematic connectivity (power supply block, MCU peripherals, sensor frontend, comms interface) and keep them physically cohesive on the PCB.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — AI infers groups from schematic. Improve: visual group boundaries and locking.
  </Accordion>
</AccordionGroup>

***

## Symbol & Footprint Generation

<AccordionGroup>
  <Accordion title="Custom symbol generation for unfamiliar ICs">
    When a part isn't in the KiCad library, generate the symbol automatically from a datasheet or description.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — Works for most ICs. Improve: scale to high-pin-count parts (900+ pins currently unreliable).
  </Accordion>

  <Accordion title="Multi-unit symbol decomposition">
    For very large ICs (900+ pins), break the symbol into logical sub-blocks (gates, power, JTAG, etc.) automatically.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span>
  </Accordion>

  <Accordion title="IPC-compliant symbol validation">
    Ensure all generated symbols pass IPC compliance checks before being added to the design.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — Improve: relax over-strict validation on complex ICs that blocks valid generations.
  </Accordion>

  <Accordion title="Footprint generation from datasheet">
    Auto-generate footprints from manufacturer datasheets when not in the standard library.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — Improve: support more package types and land pattern variants.
  </Accordion>

  <Accordion title="Library import / export">
    Import component libraries from Altium, KiCad, Cadence and export Trace's libraries to other formats.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — KiCad native. Altium and Cadence import via [EDA importers](/guides/importing-formats). Improve: download a marketplace/generated component directly into the user's EDA tool of choice with a per-user mapping table (layer mapping, aperture widths, pin-1 marker style) so it lands tool-ready.
  </Accordion>

  <Accordion title="True logic gate symbol generation">
    Generate symbols that show NAND/OR/AND gates in their traditional IEEE/IEC shapes — and decompose multi-gate parts into separable units (power/ground on the first unit) — rather than a single rectangular box. Most valued by analog, RF, and power engineers. (KiCad can display IEEE/IEC gate styles today; AI symbol *generation* currently produces a single box, so gate-level generation is the gap.)

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Part-number-driven component generation">
    Enter a manufacturer part number into a dedicated field (point-and-click, not a chat prompt), and Trace fetches the datasheet and generates the symbol + footprint automatically. Aimed at engineers who prefer point-and-click over query prompts.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Manual component editor">
    A full editor to define and tweak every symbol/footprint parameter by hand (pitch, body, pad geometry, silkscreen, pin-1 marker, thermal pad) and save to any library — the same editor that backs AI generation, so AI output can be reviewed and corrected before accepting.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span>
  </Accordion>

  <Accordion title="IPC-7351 default naming convention">
    Default generated component names to the IPC-7351 convention (per-family prefixes, dimension-encoded names), overridable by user-defined naming rules.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Batch library compliance">
    Scrub an entire library (thousands of components) against a chosen compliance rule set and component template in one pass — go-fetch datasheets, populate missing parameters (layers, aperture widths, pin-1 style, thermal vias), and flag deviations, with optional per-component confirmation prompts.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="3D model generation">
    Generate the 3D (STEP) model alongside the symbol and footprint from the same datasheet parameters.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Proprietary datasheet sourcing">
    When a datasheet isn't available via web search, point generation at a local file, Google Drive, or SharePoint — for proprietary parts whose datasheets come directly from the manufacturer.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>
</AccordionGroup>

***

## Manufacturing & Fabrication

<AccordionGroup>
  <Accordion title="Panelization support">
    Automatically arrange multiple boards on a fabrication panel with configurable mouse bites, V-scoring, breakaway tabs, and inset/offset arrangements.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Multi-fab quoting">
    Get instant quotes from multiple manufacturers (PCBWay, Pikkolo, JLCPCB, OSH Park) inline so users can compare pricing without leaving Trace.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — PCBWay and Pikkolo live. Additional fabs planned.
  </Accordion>

  <Accordion title="Configurable manufacturer DRC">
    Pull DRC rules from each manufacturer's API so designs validate against the specific fab's capabilities.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — See [manufacturer DRC presets](/guides/one-click-manufacturing#manufacturer-drc-presets). Improve: add more manufacturer presets.
  </Accordion>

  <Accordion title="DFA (Design for Assembly) validation">
    Validate designs against assembly capabilities — component density, double-sided assembly, pick-and-place tolerances — separately from DFM.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Stackup configuration">
    Specify layer count, copper weight, dielectric thickness, controlled impedance requirements, and have the AI place/route accordingly.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — Board Setup → Stackup. Improve: AI should auto-suggest stackup from signal requirements.
  </Accordion>

  <Accordion title="Component restriction filters">
    Filter component selection by grade: defense/MIL-SPEC, automotive (AEC-Q100), rad-hardened, or commercial-only.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span> — Partially supported via [.tracerules](/concepts/tracerules) ("only use automotive-grade components").
  </Accordion>

  <Accordion title="AI-powered DFM auto-correction">
    When DFM fails (clearance too small, annular ring too tight, drill size wrong), the AI proposes fixes automatically.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — AI offers to fix common violations after DRC runs. Improve: expand coverage.
  </Accordion>

  <Accordion title="Custom manufacturer integration">
    Let enterprise customers add their internal fabrication capabilities or preferred manufacturers via API.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span> — Enterprise tier
  </Accordion>

  <Accordion title="Interactive BOM viewer">
    Web-based BOM viewer with click-to-highlight on the PCB render. Share with teammates for review without needing Trace installed.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Pick-and-place visualization">
    Show component placement order and rotation on the PCB for assembly verification before sending to fab.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Multi-board projects">
    Design multiple interconnected PCBs in a single project — define board-to-board connectors and validate inter-board signals.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>
</AccordionGroup>

***

## Component Sourcing

<AccordionGroup>
  <Accordion title="Real-time stock & pricing across distributors">
    DigiKey, Mouser, Arrow, LCSC, JLCPCB integrated and visible at the BOM level.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — Improve: deeper inline BOM integration with quantity-based pricing.
  </Accordion>

  <Accordion title="Lead time forecasting">
    Surface expected delivery time for each component on the BOM, especially for parts with 26+ week lead times.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Alternative part suggestions">
    When a part is out of stock, suggest pin-compatible or footprint-compatible alternatives.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — Improve: better parametric matching and explicit "swap" workflow.
  </Accordion>

  <Accordion title="Internal inventory integration">
    For enterprise customers, integrate with the customer's internal stockroom so designs prefer in-house parts.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span> — Enterprise tier
  </Accordion>

  <Accordion title="Component lifecycle warnings">
    Alert when a chosen part is end-of-life, NRND, or being phased out.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — Partial via Nexar data. Improve: proactive alerts in BOM view.
  </Accordion>

  <Accordion title="MPN validation">
    Validate that every manufacturer part number on the BOM is real, current, and orderable before submission.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — Improve: deeper validation against distributor APIs with stock-level confidence.
  </Accordion>

  <Accordion title="BOM cost optimization">
    Given a target budget, suggest alternative components that meet specs but reduce total BOM cost. Factor in quantity breaks and distributor pricing tiers.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>
</AccordionGroup>

***

## AI / ML Capabilities

<AccordionGroup>
  <Accordion title=".tracerules — custom AI design rules">
    Define persistent rules that shape how the AI designs your circuits. Component preferences, layout conventions, manufacturing targets.

    **Status:** <span style={{color: '#16a34a'}}>Shipped (Beta)</span> — See [.tracerules documentation](/concepts/tracerules).
  </Accordion>

  <Accordion title="Engineer-specific personalization">
    The model learns each engineer's correction patterns over time so outputs adapt to individual style.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — [.tracerules](/concepts/tracerules) is the manual version. Learned personalization planned.
  </Accordion>

  <Accordion title="Reinforcement learning for placement">
    Agent learns from corrections in a simulated environment with reward functions tuned per discipline.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span>
  </Accordion>

  <Accordion title="Natural language constraints">
    Describe placement rules in plain English. LLM parses to JSON for the placement engine.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — "Keep the regulator 10mm from the MCU" works today in Agent mode.
  </Accordion>

  <Accordion title="Model fine-tuning per customer">
    Train custom model variants on a customer's specific design history and constraints.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span> — Enterprise tier
  </Accordion>

  <Accordion title="Extended thinking">
    Visible AI reasoning process with 10K-token thinking budget per step.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span>
  </Accordion>

  <Accordion title="Conversation branching">
    Try different design approaches in parallel without losing history. Fork a conversation, explore option A and option B, then merge the winner back.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Signal integrity analysis">
    AI-driven SI checks: impedance matching, crosstalk estimation, return path analysis. Integrates with IBIS models when available.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Thermal analysis">
    Heat map visualization showing power dissipation, thermal via recommendations, and copper pour optimization for heat spreading.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Power analysis">
    Voltage drop analysis, current density visualization, and power plane integrity checks.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="EMC pre-compliance">
    Basic electromagnetic compatibility checks before lab testing — loop area analysis, decoupling effectiveness, ground plane continuity.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>
</AccordionGroup>

***

## Collaboration & Teams

<AccordionGroup>
  <Accordion title="Multi-user team workspaces">
    Multiple engineers working on the same design with role-based access, version control, and design history.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — Team billing and invites shipped. Shared workspaces planned.
  </Accordion>

  <Accordion title="SSO (Okta / Azure AD / Google Workspace)">
    Enterprise single sign-on for org-level access management.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span> — Enterprise tier
  </Accordion>

  <Accordion title="Audit logs">
    Track every action on a design: who placed what, who routed what, who edited what.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span> — Enterprise tier
  </Accordion>

  <Accordion title="Real-time collaborative editing">
    Multiple engineers working on the same schematic or layout simultaneously.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Comments / annotations on designs">
    Leave notes on specific components, traces, or sections during review.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Design partner / advisor mode">
    Share read-only access with external advisors for feedback without giving full edit rights.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Design review workflow">
    Formal review process: submit design for review → reviewers annotate → approve/reject with comments → iterate. Audit trail for each review cycle.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Change request / ECO management">
    Engineering Change Orders tracked through Trace: what changed, who approved it, what's the impact on BOM/fab/assembly. Links to specific schematic/layout versions.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span> — Enterprise tier
  </Accordion>

  <Accordion title="Project handoff between teams">
    Transfer a project between engineering teams (e.g., concept team → production team) with full history, design intent, and constraints preserved.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>
</AccordionGroup>

***

## Security & Compliance

<AccordionGroup>
  <Accordion title="Self-hosted / on-premise deployment">
    For ITAR-restricted, classified, or defense-sensitive work where IP cannot leave the customer's environment.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span> — Enterprise tier
  </Accordion>

  <Accordion title="Designs stay local">
    Design files live on your machine. The AI assists via streaming connection but files never leave your control.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — This is how Trace works by default. See [How Trace Works](/concepts/how-trace-works#desktop-first-privacy-first).
  </Accordion>

  <Accordion title="No model training on customer data">
    Contractual guarantee that customer designs aren't used to train Trace's models.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — In our [Terms of Service](https://buildwithtrace.com/terms). Enterprise customers get additional contractual protections.
  </Accordion>

  <Accordion title="SOC 2 Type II compliance">
    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — Target Q3 2026
  </Accordion>

  <Accordion title="ITAR-aware deployment">
    For defense contractors handling export-controlled designs.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span> — Enterprise tier, requires self-hosted deployment
  </Accordion>

  <Accordion title="Air-gapped deployment">
    Fully offline operation with local model inference (no internet required). For SCIFs, classified environments, and locations without connectivity.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span> — Enterprise tier
  </Accordion>

  <Accordion title="IP watermarking">
    Invisible watermarks embedded in Gerber/ODB++ output that trace back to the originating engineer and organization. Detects unauthorized distribution of manufacturing files.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Role-based access control (RBAC)">
    Fine-grained permissions: viewer, editor, reviewer, admin. Control who can edit schematics, approve plans, submit to manufacturing, or access sensitive projects.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span> — Enterprise tier
  </Accordion>

  <Accordion title="Data residency controls">
    Choose where your data is stored (US, EU, APAC). Required for GDPR, data sovereignty, and certain government contracts.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span> — Enterprise tier
  </Accordion>
</AccordionGroup>

***

## Plugin Architecture

<AccordionGroup>
  <Accordion title="Altium plugin">
    Bring Trace AI capabilities into Altium Designer without forcing engineers to switch tools.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="KiCad native integration">
    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — Trace is built on KiCad. Full native integration.
  </Accordion>

  <Accordion title="Cadence Allegro plugin">
    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="OrCAD plugin">
    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Fusion 360 mechanical co-design plugin">
    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Cross-tool design transfer">
    Move designs between Trace native and any plugin-enabled tool with full fidelity.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — Altium, Cadence Allegro, Mentor PADS, and gEDA import supported via [EDA Importers](/guides/importing-formats).
  </Accordion>
</AccordionGroup>

***

## Documentation & Outputs

<AccordionGroup>
  <Accordion title="Auto-generated design documentation">
    Schematic exports, BOM PDFs, assembly drawings, fab notes generated automatically.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — BOM, Gerber, drill, pick-and-place, PDF plots. Improve: assembly drawings.
  </Accordion>

  <Accordion title="Gerber / ODB++ / IPC-2581 export">
    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — Gerber and IPC-2581 supported. ODB++ planned.
  </Accordion>

  <Accordion title="3D model export">
    Export the populated PCB as a 3D model for mechanical integration / enclosure design.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — STEP and VRML export from 3D Viewer.
  </Accordion>

  <Accordion title="Photorealistic board rendering">
    Generate visualization of the finished board for marketing or customer-facing materials.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — 3D Viewer with raytracing. Improve: one-click export workflow.
  </Accordion>

  <Accordion title="Variant-aware BOM export">
    Generate separate BOMs per design variant — different component populations for different product SKUs.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — Design variants support variant-aware exports. See [Design Variants](/concepts/design-variants).
  </Accordion>

  <Accordion title="Regulatory documentation generation">
    Auto-generate documentation packages for FDA (medical), FAA (aerospace), FCC (consumer electronics) submissions.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Component traceability">
    Track every component back to its source manufacturer and distributor lot for compliance audits.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span> — Enterprise / defense tier
  </Accordion>
</AccordionGroup>

***

## Workflow & UX

<AccordionGroup>
  <Accordion title="Plan mode with pause-and-edit">
    Pause the AI mid-generation to change parameters, flip a component, change material, then continue from there.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — Plan mode supports approve, adjust, or reject at each step.
  </Accordion>

  <Accordion title="Heavy iteration mode — plan deep before executing">
    Tell the AI to iterate extensively on the plan before touching any files. Go through multiple rounds of research, refinement, and validation before a single component is placed. For complex or high-stakes designs where you want the AI to think 10x before acting.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — Plan mode supports research + questions + approval. Improve: configurable iteration depth ("iterate 5 times on this plan before executing"), automatic re-evaluation loops, and explicit "don't touch files until I say go" constraint.
  </Accordion>

  <Accordion title="macOS, Windows, Linux native applications">
    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — All three platforms supported as of v1.3.0.
  </Accordion>

  <Accordion title="Dark mode">
    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — Dashboard supports dark mode. Desktop app uses system theme.
  </Accordion>

  <Accordion title="Keyboard shortcuts customization">
    Let users remap shortcuts to match their muscle memory from Altium / KiCad / Cadence.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — Preferences → Hotkeys. Full remapping supported.
  </Accordion>

  <Accordion title="Mobile / tablet read-only view">
    Review designs on the go without full editing.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Impedance calculator">
    Built-in stackup-aware impedance calculator for controlled impedance routing — microstrip, stripline, differential pairs.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — PCB Calculator app included with Trace. Improve: integrate directly into Board Setup.
  </Accordion>

  <Accordion title="Cross-probe improvements">
    Click a component in the schematic → instantly highlight and zoom to it on the PCB (and vice versa). AI-aware cross-probing that explains the connection context.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — Basic cross-probe works. Improve: AI-enhanced context ("this is the feedback resistor for U3's output stage").
  </Accordion>
</AccordionGroup>

***

## Developer Tools

<AccordionGroup>
  <Accordion title="CLI tool">
    Command-line interface for power users and CI/CD pipelines.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — See [CLI documentation](/resources/cli) and [CLI commands](/resources/cli-commands).
  </Accordion>

  <Accordion title="Headless mode">
    Run Trace operations programmatically without the GUI for automation.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span>
  </Accordion>

  <Accordion title="Webhook system">
    Fire events when designs reach key states (validation complete, ordered, manufactured).

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Public API">
    Let teams build custom workflows, dashboards, or integrations on top of Trace.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — Chat, downloads, auth, and manufacturer APIs available. Expanding.
  </Accordion>

  <Accordion title="Slack / Teams integration">
    Design status updates and manufacturing alerts pushed to team channels.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="GitHub integration">
    Version control for hardware designs through Git.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — Local history uses git. Improve: remote repo push/pull.
  </Accordion>
</AccordionGroup>

***

## Education & Onboarding

<AccordionGroup>
  <Accordion title="In-app tutorials">
    Guided walkthroughs for new engineers learning hardware design.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span>
  </Accordion>

  <Accordion title="University curriculum integration">
    Partner with universities to offer Trace as part of EE education.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — See [Education Program](/resources/education).
  </Accordion>

  <Accordion title="Junior engineer mode">
    Extra guardrails and explanations for engineers under 5 years of experience.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span> — Partially addressed via Ask mode's explanatory responses.
  </Accordion>
</AccordionGroup>

***

## Integration & API

<AccordionGroup>
  <Accordion title="Jira / Linear integration">
    Track PCB design tasks alongside firmware/software issues in the same project tracker.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Custom manufacturer API integration">
    Enterprise customers add their internal fab capabilities via API.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span> — Enterprise tier
  </Accordion>
</AccordionGroup>

***

## Known Issues Being Addressed

| Issue                                             | Status                                                                                      |
| ------------------------------------------------- | ------------------------------------------------------------------------------------------- |
| High-pin-count symbol generation (900+ pins)      | In progress — multi-unit decomposition                                                      |
| Plan mode timeout on large schematics             | Fixed in 1.3.0 (extended timeouts + progress reporting)                                     |
| Windows refocus bug (AI steals window focus)      | Fixed in 1.3.0                                                                              |
| Token efficiency on broad queries                 | Improved in 1.3.0 (better context scoping)                                                  |
| PCBWay ConfirmOrder API failures                  | Fixed in 1.3.0                                                                              |
| Schematic title persists when starting a new chat | Investigating — AI inherits context from the project title which can bias new conversations |

***

<Note>
  This list is community-driven and updated regularly. Features are prioritized by user votes, beta tester feedback, strategic alignment, and engineering feasibility. Timelines are estimates, not commitments.
</Note>

***

## How Requests Get Prioritized

1. **Vote on Discord** — Requests with the most upvotes in **#feature-requests** get reviewed first
2. **Beta feedback** — Active beta testers who report bugs and test features get their requests fast-tracked
3. **Design partner calls** — Engineers who join advisory calls provide direct input on priorities
4. **Strategic alignment** — Some features unlock entire categories of users or markets

## Join the Beta

The fastest way to influence what gets built: [apply for the beta program](/resources/beta). You get:

* Free Trace access (all AI modes, no subscription needed)
* Direct line to the engineering team
* Your bugs and requests prioritized
* Points for feedback, redeemable for swag and extended access

Apply from your [dashboard](https://buildwithtrace.com/dashboard/beta).

***

## Community-Derived Requests

Extracted from Discord conversations, Twitter discussions, and user feedback sessions.

<AccordionGroup>
  <Accordion title="Symbol style preference (NEMA/IEEE vs IEC)">
    Configurable symbol rendering per project — US-style resistors (zigzag) vs EU-style (rectangle), ground symbols, etc. Engineers working across regions or for international clients need to switch seamlessly.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — KiCad 10 supports both IEEE and IEC styles in Preferences. Improve: per-project style lock via [.tracerules](/concepts/tracerules) so AI generates consistent symbols.
  </Accordion>

  <Accordion title="AI schematic review with actionable suggestions">
    Upload or open a schematic and get detailed design review feedback: wake-up pin selection, I2C address flexibility (pull-up/down options), spare IO breakout to headers, connector standard recommendations (STEMMA/QWIIC), LED current optimization, and power path alternatives.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — Ask mode provides general review. Improve: structured checklist output with specific pin/component recommendations.
  </Accordion>

  <Accordion title="LED resistor and current calculator">
    Built-in calculator for LED series resistor values, forward voltage lookup, and current limiting. Support for RGB LEDs, low-current alternatives, and brightness matching.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span> — Partially supported via Ask mode. Dedicated inline calculator planned.
  </Accordion>

  <Accordion title="Power path topology suggestions">
    AI recommends power path management approaches: ideal diodes (TI LM66200), eFuses, load switches, OR-ing controllers based on the design's power requirements, battery chemistry, and fault protection needs.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — Supported via Ask mode and parts search. Improve: proactive suggestions when power input topology is detected.
  </Accordion>

  <Accordion title="I2C address configuration helper">
    When adding an I2C device, suggest pull-up/pull-down resistor options for address pins to enable flexibility. Flag potential address conflicts when multiple I2C devices share a bus.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Connector recommendation engine">
    Given requirements (pin count, current, stack height, cost target, assembly method), recommend the best connector family: mezzanine B2B, FFC, card edge, JST SH/STEMMA, or 2.54mm headers. Factor in assembly difficulty and failure modes.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="3D model generation from datasheet dimensions">
    Auto-generate STEP files from package dimensions in a datasheet. No more hunting for 3D models or manually creating them in FreeCAD for every non-standard part.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Harsh environment DFM suggestions">
    Detect designs intended for harsh environments (outdoor, water-adjacent, high-vibration) and suggest conformal coating, potting, strain relief, and mechanical fastening beyond just solder joints.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="FCC / CE compliance guidance">
    When a design uses RF (WiFi, BLE, LoRa), provide compliance guidance: FCC 15b (unintentional radiator) for the PCB, FCC 15c (intentional radiator) for custom RF, and when pre-certified modules eliminate the need for full testing.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span> — Partially covered in Ask mode for general questions.
  </Accordion>

  <Accordion title="Multi-MCU programming flow">
    Support designs where a primary MCU (ESP32) programs secondary MCUs (ATtiny, RP2040, PSoC) via UART/SPI during boot. Help with ISP pin routing, boot mode selection, and firmware partition planning.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Firmware-aware pin assignment">
    When assigning MCU pins, prioritize wake-up capable pins for interrupt inputs, ensure boot/ISP pins aren't conflicting, and flag when high-speed peripherals are assigned to non-optimal pins.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — Signal path tracing helps. Improve: explicit pin capability awareness from MCU datasheets.
  </Accordion>

  <Accordion title="Programmable logic alternatives (GreenPAK, CPLD)">
    When a design uses multiple discrete logic gates or 555 timers, suggest compact programmable logic alternatives like Renesas GreenPAK or small CPLDs that reduce BOM count and board space.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Via-in-pad recommendations">
    When routing tight-pitch components (BGA, QFN) or high-speed USB/HDMI, proactively suggest via-in-pad with backfill, and flag the additional manufacturing cost.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span> — Supported via prompting. Automatic detection planned.
  </Accordion>

  <Accordion title="Regional manufacturer database">
    Support fabs beyond China and US: PCBPower (India), Eurocircuits (EU), Würth (Germany), local shops. Engineers choose local for communication, lead time, and avoiding import duties.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span> — PCBWay and Pikkolo shipped. More fabs coming.
  </Accordion>

  <Accordion title="PCB art and silkscreen graphics">
    Import SVG logos, mascots, and artistic silkscreen designs with proper conversion to copper/silkscreen layers. One-click import that handles DRC-safe minimum line widths.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — KiCad supports SVG import to silkscreen. Improve: AI-assisted placement and DRC-safe scaling.
  </Accordion>

  <Accordion title="Protocol-specific reference designs">
    Templates for common interfaces: LoRa + GPS tracker, USB-C PD sink, CAN bus node, BLE beacon, ESP32 base station, RP2040 minimal. Pre-validated schematics with correct antenna matching, decoupling, and crystal placement.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span> — Partially available via Ask mode reference suggestions.
  </Accordion>

  <Accordion title="RF antenna matching wizard">
    Pi-filter value calculation from NanoVNA measurements or target impedance. Smith chart visualization, matching network topology selection (L, Pi, T), and component value optimization with standard E-series values.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Thermal via array generation">
    For high-power components (voltage regulators, FETs, LEDs), auto-generate thermal via arrays under exposed pads with configurable pitch, drill size, and connection to internal copper pours.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Real-time BOM cost tracking">
    Show running total BOM cost as you add components, with quantity-break pricing visible. Alert when a component pushes the total beyond a target budget.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="PCBA panelization optimizer">
    Given board dimensions and fab minimum panel size, calculate optimal panelization (1x2, 2x2, 1x3) to minimize waste and cost. Account for JLC/PCBWay panel constraints and rail requirements.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Open hardware template library">
    Curated, proven open-source reference designs: Bitcoin miner boards, VR trackers, IoT sensors, motor controllers, drone flight controllers. Fork and customize instead of starting from scratch.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span> — See [PCB Marketplace](#coming-soon) (Coming Soon).
  </Accordion>

  <Accordion title="Gamified learning path for software engineers">
    Guided onboarding for software developers transitioning to hardware: start with basic circuits (LED + resistor), progress through power supplies, MCU breakouts, and multi-layer designs. Progress tracking, achievements, and community challenges.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — See [Education Program](/resources/education). Improve: in-app guided progression.
  </Accordion>

  <Accordion title="Hand soldering assembly guide">
    For hobbyist/prototype boards: suggest component placement order for hand soldering (smallest first, heat-sensitive last), generate a visual assembly guide with numbered steps, and flag components that require reflow.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Community design showcase">
    Gallery of real boards designed and manufactured through Trace. Filterable by complexity, use case, and components used. Engineers can share their work and inspire others.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — Discord showcase channel active. In-platform gallery planned.
  </Accordion>

  <Accordion title="Freelance / contract design marketplace">
    Connect PCB designers with companies needing custom boards. Skill verification, portfolio showcase, escrow payments, and NDA management. Bridge the gap between experienced designers and companies with hardware needs.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span> — See [PCB Marketplace](#coming-soon) (Coming Soon).
  </Accordion>

  <Accordion title="X-ray inspection defect detection">
    Upload X-ray images of assembled boards and get AI-assisted defect detection: tombstoning, bridging, cold joints, missing components, BGA voiding.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Stencil aperture optimization">
    Auto-modify stencil apertures based on component type: reduce for fine-pitch QFP to prevent bridging, enlarge for thermal pads, add home-plate shapes for BGA. Export optimized stencil Gerber separately.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Wire harness / cable design">
    Design board-to-board and board-to-external cable harnesses: connector pinout mapping, wire gauge selection, crimp terminal specification, and IDC cable generation. Export cable assembly drawings.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Zephyr RTOS pin mapping integration">
    When using an MCU with Zephyr support, auto-generate devicetree pin mappings from the schematic. Ensure pin assignments are compatible with Zephyr driver requirements.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Low-power budget estimation">
    Estimate total power consumption from BOM — pull sleep/active current from datasheets, calculate battery life for different duty cycles, and flag components with high quiescent current that break a power budget.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Breakout board auto-generation">
    From an MCU schematic, auto-generate a breakout board: route all unused GPIO to standard 2.54mm headers, add STEMMA/QWIIC connector for I2C, expose SWD/JTAG, and include USB-C for power/programming.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Assembly difficulty scoring">
    Flag components that can't be hand-assembled (BGA, 0201, QFN with exposed pad) and score the board's overall assembly difficulty. Suggest alternatives when targeting home/prototype assembly.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Level translator suggestions for legacy interfacing">
    When mixing voltage domains (3.3V MCU to 5V/12V legacy IO), auto-suggest level translators, voltage dividers, or open-drain configurations based on signal direction and speed requirements.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — Supported via Ask mode. Automatic detection of voltage domain mismatches planned.
  </Accordion>

  <Accordion title="Manufacturing constraint-aware board outline">
    When a target PNP machine or panel constraint is specified (e.g., 220mm max conveyor width), enforce board outline limits during design and suggest panelization that fits.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Standard expansion connector pinouts">
    When adding I2C/SPI/UART expansion, suggest standard pinout conventions (STEMMA/QWIIC for I2C, Pmod for SPI) so boards are compatible with the broader ecosystem of breakout modules.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Surface finish auto-selection">
    Based on connector types and pad requirements (card edge needs gold fingers, fine-pitch BGA needs ENIG, hobby boards can use HASL), suggest the optimal surface finish and flag cost implications.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Production yield estimation">
    Given component count, pad pitch, and assembly method, estimate first-pass yield and rework rate. Help engineers understand the manufacturing risk of their design complexity.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Multi-fab instant cost comparison">
    Show side-by-side pricing from JLC, PCBWay, Pikkolo, OSH Park, and local fabs for the current board — including shipping, assembly, and lead time. Engineers currently get quotes one-at-a-time.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — PCBWay and Pikkolo quotes live. Multi-fab comparison view planned.
  </Accordion>

  <Accordion title="Mechanical shock and vibration DFM">
    Analyze connector choices and component mounting for shock/vibration environments. Flag 2.54mm headers that disconnect on drop tests, suggest locking connectors, and recommend reinforcement strategies.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="EasyEDA project import">
    Import EasyEDA / LCEDA projects directly into Trace with full symbol, footprint, and routing preservation. Many engineers start in EasyEDA for JLC integration and want to migrate to a more capable tool.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="PIO / peripheral template generation">
    For RP2040 PIO, ESP32 RMT, and similar programmable peripherals, generate configuration code from timing diagrams or protocol descriptions. Bridges the gap between hardware routing and firmware initialization.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Interconnect method comparison tool">
    Given two PCBs that need to connect, compare options (FFC, B2B mezzanine, card edge, wire harness, castellated edge) across cost, pin count, reliability, insertion cycles, and assembly difficulty.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Monthly design challenges">
    Community competitions with specific constraints (smallest board, lowest BOM cost, most creative silkscreen, fastest route). Builds engagement and provides real-world practice for learners.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Anonymous portfolio sharing">
    Share PCB designs publicly without revealing your real identity. Engineers at companies with strict IP policies want to showcase personal work without linking to their employer's GitHub.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Home / small-batch assembly workflow">
    End-to-end guide: stencil ordering, paste application, PNP programming (NeoDen K8, LumenPnP), reflow profile setup, and through-hole selective soldering. Trace exports optimized for each step.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Castellated module design support">
    Design modules with castellated edges for board-to-board soldering. Auto-generate the half-via edge pattern, test points, and pick-and-place compatible panels.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — KiCad supports castellated pads. Improve: AI-assisted module breakout with auto-generated carrier board.
  </Accordion>

  <Accordion title="Sensor fusion reference designs">
    Templates for IMU + gyro + magnetometer boards with Kalman filter firmware scaffolding. Pre-validated layouts for BMI270, ICM-42688, BMM350 with correct decoupling, mounting orientation markers, and CAN/SPI output.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="AI logo / artwork conversion for PCB">
    Upload a logo image and auto-convert to DRC-safe silkscreen or copper artwork. Handle minimum line widths, simplify complex vectors, and preview at fabrication resolution. No more hours in Inkscape.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Component library manager with database backend">
    Manage thousands of components with lifecycle status, preferred suppliers, company-specific metadata. Altium-style database library without the Altium price tag. Team-shared with version control.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Ground plane continuity checker">
    Visualize return paths, flag ground plane splits under high-speed traces, and identify areas where via stitching is needed. Color-code ground plane connectivity per net.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="3D stack height calculator">
    When designing multi-PCB stacks, calculate total height from PCB thickness + component height + connector mating height. Flag interference with enclosure constraints.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Rework procedure generation">
    For assembled boards needing fixes, generate step-by-step rework procedures: required tools, temperature profiles, component removal sequence, and re-soldering guidance for specific package types.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="PNP feeder slot optimizer">
    Given a PNP machine's feeder capacity (e.g., 66 slots at 8mm, fewer for wide components), plan which components go in feeders vs IC trays, and suggest BOM optimizations to fit within machine constraints.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="LoRa + GPS antenna placement guidance">
    For combined LoRa/BLE + GNSS boards, guide antenna placement: ground plane keep-outs, separation distance, matching network layout, and coexistence best practices for RAK, Quectel, u-blox modules.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Modular rack-mount / 19-inch design templates">
    Templates for modular systems: DIN rail, 19" rack, Eurocard form factors with standard connector positions, front panel design, and backplane interconnect planning.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Motor / power switching circuit templates">
    Pre-validated circuits for H-bridge, half-bridge, ideal diode ORing, hot-swap, inrush limiting, and reverse polarity protection. Sized for common voltage/current ranges with FET selection guidance.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Budget-optimized component suggestions">
    Given a target BOM cost, suggest the cheapest working solution for each functional block. "I need a voltage regulator, JLCPCB-stocked, under \$0.10" → ranked suggestions with tradeoff notes.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — Parts search shows pricing. Improve: explicit budget constraint mode.
  </Accordion>

  <Accordion title="CNC-millable PCB design mode">
    For home prototyping with CNC routers: enforce minimum trace widths for milling, single/double layer only, avoid features requiring chemistry (plated vias), and generate isolation routing G-code.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Ultra-compact wearable design mode">
    Constraints for wearable electronics: max board dimensions, flex PCB support, battery placement optimization, low-profile component enforcement, and weight estimation.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Energy harvesting reference designs">
    Solar MPPT, piezo harvesting, thermal (TEG) circuits with ultra-low-power management ICs (BQ25570, SPV1050). Pre-validated for common panel sizes and indoor/outdoor light levels.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Shortage-proof BOM (multi-source)">
    For each critical component, auto-suggest 2-3 pin/footprint-compatible alternatives from different manufacturers. Generate a "plan B" BOM that can be swapped without board respin.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — Alternative part suggestions exist. Improve: explicit second-source BOM column.
  </Accordion>

  <Accordion title="Metric / imperial size code translator">
    Show both naming conventions inline: 0402 (imperial) = 1005 (metric). Auto-convert based on user preference. Eliminate confusion when datasheets and fab houses use different systems.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="BOM-to-schematic reverse generation">
    Given a BOM (component list with values and package sizes), generate a plausible schematic interconnection. For cases where a client provides parts but no design — the AI infers the circuit topology.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="DXF board outline import with keep-out zones">
    Import mechanical board outlines from DXF/STEP with automatic keep-out region detection (mounting holes, connector cutouts, height restrictions) and snap to grid.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — KiCad supports DXF import. Improve: auto-detect keep-outs from mechanical model features.
  </Accordion>

  <Accordion title="LED / display driver circuit templates">
    Pre-validated circuits for driving 7-segment displays, LED matrices, NeoPixel/WS2812 strips, and OLED modules. Include shift register cascading, PWM driver selection, and current budgeting.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Debug / programming infrastructure auto-generation">
    Auto-add SWD/JTAG headers, UART debug ports, serial MUX for multi-MCU ISP, and test points on critical signals. Configurable between "full debug" (development) and "minimal" (production) variants.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — Partially via Agent mode. Dedicated debug infrastructure tool planned.
  </Accordion>

  <Accordion title="PoE (Power over Ethernet) design wizard">
    Select PoE class (802.3af/at/bt), configure PD interface IC, isolation transformer, and DCDC converter. Auto-generate the compliant circuit with proper thermal derating for the chosen wattage.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="Automotive / avionics design templates">
    Pre-configured for harsh environments: automotive temp ranges (-40 to +125C), AEC-Q100 component filtering, CAN/LIN bus circuits, and DO-254 documentation scaffolding for avionics.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Interactive real-time simulation (MultiSIM-style)">
    Live circuit simulation with draggable parameter sliders, virtual oscilloscopes, voltage/current sources, and probes. Tweak a resistor value and see the output waveform change in real-time. A digital breadboard that makes analog design intuitive — especially for students learning op-amp configurations, filters, and power supplies.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span> — Transformative for education and rapid prototyping. Research phase.
  </Accordion>

  <Accordion title="BGA escape routing">
    AI-assisted fan-out from dense BGA packages. Learn escape patterns from manufacturer reference designs (Xilinx, NXP, TI) and generate layer-by-layer breakout routing with proper via transitions and impedance continuity.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Test instrument integration (logic analyzer, oscilloscope)">
    Connect open-source instruments (Saleae, DSLogic, Analog Discovery) to test points on your board. Ask "my SPI looks wrong, what's happening?" and Trace captures signals, decodes protocols, and diagnoses issues using the schematic as context.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Auto-generate test firmware">
    Generate purpose-built firmware to exercise specific signals for board bring-up: toggle GPIOs, generate SPI/I2C traffic, sweep DAC outputs, measure ADC inputs. Flash it, verify hardware, then load production firmware.

    **Status:** <span style={{color: '#6b7280'}}>Requested</span>
  </Accordion>

  <Accordion title="FPGA design support (Vivado / Yosys)">
    Support FPGA-based designs: pin planning with constraint file generation, clock domain visualization, block RAM inference, and MCP bridge to Vivado/Yosys for synthesis feedback. Target both commercial (Xilinx/AMD) and open-source (iCE40, ECP5) toolchains.

    **Status:** <span style={{color: '#6366f1'}}>Planned</span>
  </Accordion>

  <Accordion title="Datasheet reference design auto-import">
    Point to a chip datasheet and auto-extract the recommended application circuit — all supporting components (decoupling caps, crystal, pull-ups, boot resistors, programming header) added in one shot. Learn from TI, STMicro, NXP reference designs.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — Datasheet parsing extracts circuits. Auto-import to schematic planned.
  </Accordion>

  <Accordion title="Design error detection (topology-aware)">
    Flag circuit mistakes that require domain knowledge: driving MOSFETs in linear region from weak GPIO, missing gate drivers, incorrect bias networks, capacitive loading on high-impedance nodes, ground loops in mixed-signal designs.

    **Status:** <span style={{color: '#ca8a04'}}>In Progress</span> — ERC catches basic errors. AI-powered topology-aware detection planned.
  </Accordion>

  <Accordion title="Unpopulated component slots for design flexibility">
    Support intentionally empty footprints for debug/production variants: optional pull-ups, alternative filter values, test points, jumper resistors. Track which slots are intentional vs accidentally missing.

    **Status:** <span style={{color: '#16a34a'}}>Shipped</span> — KiCad supports DNP (Do Not Populate) marking. Improve: AI suggests where flexibility slots would be valuable.
  </Accordion>
</AccordionGroup>