> ## Documentation Index
> Fetch the complete documentation index at: https://docs.buildwithtrace.com/llms.txt
> Use this file to discover all available pages before exploring further.
# PCB Layout
> The PCB editor is where you arrange components and route traces on your physical board.
## Editor Overview
The PCB editor includes:
* **Layer stack** — Manage copper, silkscreen, mask, and mechanical layers
* **Ratsnest** — Visual guides showing unrouted connections
* **3D Viewer** — Preview your board in 3D (`Alt+3`)
* **Design rules** — Configurable constraints for trace width, clearance, etc.
* **[DRC Rule Editor](/concepts/drc-rule-editor)** — Visual rule builder for creating and managing design rules with autocomplete and constraint panels
### AI Layer Control
Ask the AI to switch between PCB layers, apply layer presets, or toggle layer visibility directly from the chat. For example, "switch to the back copper layer" or "hide all silkscreen layers." The AI uses dedicated tools (`switch_layer`, `get_layers`, `apply_layer_preset`, `set_layer_visibility`) to control the layer stack.
## Component Placement
After importing from the schematic (`F8`), arrange components on the board:
* **Move** components with `M`
* **Rotate** with `R`
* **Flip** to the back side with `F`
* Group related components together
* Keep high-frequency components close to their connections
* Align connectors with board edges
### AI Auto-Placement
Trace includes an AI-powered auto-placer that combines LLM-guided constraint analysis with simulated annealing and graph neural network-based reinforcement learning. The system analyzes your schematic to understand component connectivity, signal flow, and relationships, then optimizes component positions.
* **Import optimization** — Import existing KiCad boards and let the AI optimize component placement, especially effective for boards where placement was done manually and could benefit from optimization
* **Signal flow analysis** — The GNN learns component connectivity patterns to place related components close together
* **Constraint-aware** — Respects board outline, keep-out zones, and mechanical constraints during optimization
* **EMI-aware placement** — The placer considers electromagnetic interference when positioning sensitive analog and high-speed digital components, keeping noisy components away from sensitive inputs (expanding)
You can ask the AI to place all components or just a specific group.
#### How It Works
The placement engine uses a multi-stage approach:
**Production (live today):**
1. **LLM constraint analysis** — Claude analyzes your schematic to identify functional groups, critical nets, thermal constraints, edge-component requirements, and proximity rules.
2. **LLM floorplan generation** — Multiple floorplan variants are generated, seeding components into logical regions before SA begins.
3. **Simulated annealing** — A calibrated SA optimizer with 8 move types (translate, rotate, swap, group move, centroid pull, mirror, perturb) iterates through thousands of placement candidates. The cost function incorporates HPWL wirelength, RUDY congestion estimation, group compactness, thermal distribution, and overlap penalties.
4. **LLM candidate evaluation** — Claude evaluates multiple SA-optimized candidates and selects the winner based on signal integrity, manufacturability, and constraint satisfaction.
**In training (transitioning to production):**
1. **Graph encoding** — Your netlist is represented as a bipartite component-net graph. A 4-layer GraphSAGE encoder (256-dim, trained with self-supervised objectives: incidence prediction, functional classification, placement proxy, and masked reconstruction) produces topology-aware component embeddings.
2. **RL placement** — A Soft Actor-Critic (SAC) agent, guided by frozen GNN embeddings, makes sequential placement decisions with curriculum learning (starting on small boards, graduating to complex ones). Trained on synthetic PCB data generated from parameterized board templates.
3. **Physics-informed cost** — The reward function incorporates HPWL, congestion, thermal distribution, and constraint violations, inspired by approaches from our advanced cloud engine and GPU-accelerated physics-informed EDA research.
This approach has been validated in research on 15 real-world KiCad PCBs ranging from 5 to 681 components, achieving measurable wire length improvements over unguided simulated annealing.
The auto-placer is under active development. The production LLM + SA pipeline handles placement with multi-objective optimization today. The GNN + RL pipeline is in active training on AWS/GCP GPU instances, targeting production deployment as it achieves reliable performance across board complexity ranges. The roadmap includes deeper constraint awareness — decoupling capacitor proximity, functional group clustering, EMI separation zones, thermal management, and enclosure fit. See the [GNN Placement FAQ](/resources/faq#ai--technology) for more details.
## Design Variants
Manage alternate board configurations without duplicating your project. Define variants to control which components are populated, swap values, or change footprints for different product SKUs, regions, or development stages.
See the [Design Variants](/concepts/design-variants) page for details on creating variants, exporting with `--variant`, and importing Altium variants.
## Routing
Route traces manually or use the autorouter:
* Press `X` to start routing a trace
* Press `V` to place a via and switch layers
* The autorouter handles all connections automatically
* Manual routing gives you full control over trace paths
### Routing engines: Quick vs Advanced
Trace offers two AI layout engines. Just ask the assistant to route (or place) your board and it picks the right one — or tell it which you want.
* **Quick routing (free):** Fast cloud autorouting for all plans. Best for ordinary "route the board" requests. No credits required. You can request a specific track width — *"autoroute with 0.5mm tracks"* — and the router uses it instead of the board's net class defaults (the AI confirms the width it applied).
* **Advanced layout (paid):** AI-driven placement and routing powered by our advanced cloud engine. It can auto-**place** components, auto-**route**, or do **both**, optimizing across the whole board over a few minutes. Your `.kicad_pcb` is sent to the cloud engine and the optimized board is returned.
Advanced layout requires a **paid plan** and **Layout Credits** (paid users get one free layout to try it). Trial and free plans can use quick routing only. See [Billing](/guides/billing#layout-credits) for credits.
## Layer Stackup & Impedance Control
These features are experimental and under active development.
For controlled-impedance designs, Trace follows a stackup-first workflow:
1. **Define the stackup** — Set layer count, copper weight, and dielectric thickness for your board
2. **Derive trace widths** — Trace calculates trace widths for controlled impedance based on your stackup parameters
3. **Lock before routing** — Impedance-controlled widths are locked into net classes before routing begins, so traces maintain correct geometry throughout the layout
### Differential Pairs
Differential pairs (USB, LVDS, DDR, PCIe) are handled with dedicated constraints:
* **Coupled routing** — Diff pairs are routed together with controlled spacing enforced during routing
* **Length matching** — Intra-pair and inter-pair length matching to maintain signal timing
* **Reference plane tracking** — Return paths are tracked to keep them continuous across the reference plane, avoiding splits that degrade signal integrity
### Signal Integrity Considerations
* High-speed nets are identified from the schematic and flagged for priority routing
* Via stitching near signal transitions between layers
* Copper pour optimization for thermal and EMI performance
## Length Tuning & Matched Length Groups
For timing-critical interfaces (DDR, USB, PCIe, parallel buses), Trace lets you tune individual trace lengths and match a whole group of nets to a shared target.
**Length tuning** inserts serpentine (meander) shapes to add length to a trace:
* **Tune Length of a Single Track** (`7`)
* **Tune Length of a Differential Pair** (`8`)
* **Tune Skew of a Differential Pair** (`9`)
The live status overlay shows the current length, the target, and how far you are from it (green when in range, red when out).
### Matched Length Groups
Matched Length Groups are in active alpha. The feature is functional and shipping, but the UI, API surface, and DRC integration may change as we iterate based on early feedback.
A **Matched Length Group** is a first-class object saved with your board that ties a set of nets together so they stay length-matched. It is the missing piece between per-trace tuning and a whole matched bus.
* **Shared target, derived automatically** — match every member to the **longest** member (the default, so you never have to type a target), to an **explicit** length, or to a **matched-length DRC constraint**.
* **Configurable tolerance** and optional **time-domain (propagation-delay)** matching instead of physical length.
* **Series components handled** — a member "signal" can span multiple physical nets, e.g. a signal split by a series termination resistor (source pin → resistor → destination pin). Each net contributes its pad-to-pad routed path length (stubs and branches are excluded; via/stackup height and pad-to-die length are included), and the signal length is the sum. Branched/multi-load nets that don't form a single pad-to-pad path fall back to net-total length and are marked approximate.
* **Live status** — an overlay lists each signal's current length, the shared target, and the per-signal delta, colored by whether it is within tolerance.
* **DRC-aware** — any member out of tolerance is flagged by the Design Rule Checker.
Select traces from the nets you want to match (a bus, a diff-pair group, or signals through series resistors).
Use **Route → Create Matched Length Group**, the track-tuning toolbar, or right-click the selected nets in the **Net Inspector → Create Matched Length Group**.
The status overlay shows each signal's current length, the shared target, and its delta. Edit the target policy, tolerance, or time-domain setting in the **Properties** panel.
Tune any member net (**Tune Length of a Single Track**, `7`) — the tuner automatically uses the group's shared target, so meandering matches the trace to the group.
The matched-length **rule** (target/tolerance/skew) is defined in the [DRC Rule Editor](/concepts/drc-rule-editor); the group above is the interactive workflow for hitting it.
### AI length matching
You can also ask the assistant to do it. The `match_lengths` tool creates and manages matched length groups from a prompt:
* *"Length-match the DDR3 DQ group within 5 mil."*
* *"Match these nets, accounting for the series resistors."*
It accepts grouped nets (including signals split across series components), a target policy, tolerance, and time-domain matching. By default it creates the group so you can tune interactively; an opt-in mode also places the meanders automatically.
## Design Rule Check
Run DRC to verify your layout meets manufacturing constraints:
* Minimum trace width and spacing
* Via drill sizes and annular rings
* Courtyard clearances between components
* Board edge clearances
* Impedance rule violations
* Unrouted nets
* **Track endpoints not centered on via** — Detects misaligned track-to-via connections from the interactive router (new in Trace 1.3)
Access via **Inspect → Design Rules Checker** or `Ctrl+Shift+D`.
For creating and managing design rules visually, see the [DRC Rule Editor](/concepts/drc-rule-editor).
## Copper Pours
Add copper fill zones for ground planes and power distribution:
1. Press `Ctrl+Shift+Z` to add a filled zone
2. Select the net (usually GND)
3. Draw the zone boundary
4. Press `B` to fill all zones
Zones with different priorities can now be merged, allowing overlapping copper pours to combine when they share the same net. Negative outset values are supported for insetting zone boundaries, and negative silkscreen clearance values are allowed for designs that intentionally overlap silkscreen and copper.
## Track & Via Properties
The Track & Via Properties dialog includes **backdrill sizes** for controlled-depth drilling. Backdrill removes unused via stubs that can cause signal reflections on high-speed designs.
## Manufacturing Export
### IPC-2581
IPC-2581 export includes several enhancements:
* **BomRef and AvlRef elements** — Approved vendor list references in the output
* **Board profile cutouts** — Internal cutouts included in the board profile
* **Multi-outline geometry merging** — Complex component outlines merged correctly
* **Pin 1 orientation inference** — `pinOneOrientation` automatically inferred from pin 1 position
* **Stable reference designators** — Synthesized stable refdes for components with empty references
* **Schematic revision for BOM** — Uses schematic revision metadata in BOM output
### Standard Exports
Generate Gerbers, drill files, pick-and-place files, and BOMs. Package into fab-ready ZIP archives. Export STEP files for mechanical CAD integration. All exports support the `--variant` flag for [design variant](/concepts/design-variants) filtering.
## Case Design Import
Import your enclosure design to use as a reference layer while designing your PCB. This lets you align mounting holes, connectors, and components with your physical case before manufacturing.
### Supported Formats
* **DXF** — 2D outline from CAD software (Fusion 360, SolidWorks, FreeCAD)
* **STEP/STP** — 3D models for full enclosure visualization
### Use Cases
* Align USB ports, buttons, and LEDs with case cutouts
* Position mounting holes to match enclosure standoffs
* Verify antenna keep-out zones for Bluetooth/WiFi
* Check battery compartment clearances
* Ensure component height fits within enclosure
## Importing from Other EDA Tools
Trace can import PCB layouts from Cadence Allegro (including v18+ binary format), Mentor PADS (ASCII format), and Altium Designer. See the [Importing from Other EDA Tools](/guides/importing-formats) guide for details.