> ## Documentation Index
> Fetch the complete documentation index at: https://docs.buildwithtrace.com/llms.txt
> Use this file to discover all available pages before exploring further.

# DRC Rule Editor

> Visual rule builder for defining and managing PCB design rules with constraint panels, custom expressions, and autocomplete.

## Overview

The DRC Rule Editor is a visual interface for creating and managing PCB design rules. Instead of writing custom rule expressions from scratch, you build rules by selecting constraint types, setting values, and defining conditions through dedicated panels.

Access the DRC Rule Editor from **Inspect → DRC Rule Editor** in the PCB editor.

<Note>
  The DRC Rule Editor was introduced in Trace 1.3 (built on KiCad 10). It provides a graphical alternative to hand-writing `.kicad_dru` custom rule files.
</Note>

## Constraint Types

Each rule targets a specific constraint type. The editor provides dedicated panels for each:

### Clearance

Set minimum spacing between copper objects (tracks, pads, vias, zones). Define different clearances for different net classes or specific net-to-net pairs.

### Track Width

Set trace width rules using an **optimum width** with **+/- tolerance** values. This lets you define a target width while allowing the router flexibility within your acceptable range. The DRC flags violations outside the tolerance band.

### Via Style

Configure via size rules including drill diameter, annular ring, and pad size. Micro-via (uVia) constraints are consolidated into this panel — set separate rules for standard vias and micro-vias in the same place.

### Matched Length

For timing-critical signals (DDR, USB, PCIe), set length matching constraints with:

* **Target length** — The nominal trace length
* **Tolerance** — Acceptable deviation from target
* **Skew** — Maximum allowed length difference between members of a differential pair

To interactively match a group of nets to a target (with a live status overlay), see [Length Tuning & Matched Length Groups](/concepts/pcb-layout#matched-length-groups).

### Text Height & Thickness

Control silkscreen and fabrication layer text with minimum height and stroke thickness rules. Useful for ensuring reference designators and labels meet your fab house's readability requirements.

### Courtyard Clearance

Set minimum spacing between component courtyards. The editor includes a bitmap reference showing courtyard regions to help visualize what the rule controls.

## Custom Expressions

For rules that can't be expressed through the standard panels, the editor includes a custom expression input with **Scintilla-based autocomplete**. Start typing a property name or function and the editor suggests completions:

* Object properties like `A.NetClass`, `B.Type`, `A.Pad_Size`
* Functions like `isPlated()`, `inDiffPair()`, `memberOf()`
* Operators and comparison syntax

The autocomplete understands the DRC expression grammar and only suggests valid completions in context.

## Rule Management

### Naming and Validation

Each rule has a unique name. If you create a rule with a name that already exists, the editor warns you and offers to merge the rules. This prevents accidental duplicates that could create conflicting constraints.

### Dynamic Unit Labels

Constraint value fields display units dynamically based on your project settings (mm, mils, inches). Change the project units and the rule editor updates all labels automatically.

### Keyboard Shortcuts

| Shortcut   | Action         |
| ---------- | -------------- |
| **Ctrl+S** | Save all rules |

### Scrolling

For large rule sets, the editor content panel scrolls vertically. Rules are organized by constraint type, so you can quickly find and edit specific rules even in complex designs.

## Workflow

A typical workflow for setting up design rules:

1. Open the DRC Rule Editor from **Inspect → DRC Rule Editor**
2. Add rules for each constraint type your design requires
3. Set values based on your fab house's capabilities (e.g., 6mil min clearance, 5mil min trace width)
4. Use custom expressions for advanced conditions (e.g., different clearances for high-voltage nets)
5. Save with **Ctrl+S**
6. Run DRC (**Inspect → Design Rules Checker** or `Ctrl+Shift+D`) to validate your layout against the new rules

Rules persist in the project and apply every time DRC is run. The AI also respects your custom rules when making layout changes.